I know many wise men has said NO NO, but1)
Lattice engineer suggest that it works (assumable reliable) on machXO
the IO technology between machXO and Xilinx FPGAs isnt so big so I wonder why cant it be done with Xilinx ?
for what I see is following25MHz crystal 27p caps 560 series 1M parallel
when using LVCMOS33 SLEW=FAST
then there is some sort of overdrive, that makes oscillation to periodically stop and restart200 us work then 75 idle, then restarts again, the FPGA input sees however nice 25MHz from the crystal ALL time, (also when the output doesnt swing)
by simply changing slew=slow the circuit does start work reliable.
so any technical reasons why this circuit can not (should not) be used??
crystal vs oscillator price difference is still some 0.30 USD, so why waste the pennies