2 leg crystal on FPGA: Lattice vs Xilinx

Antti,

The circuit works, only because the IO acts like an inverter with a very small delay.

If the IO has more delay, than the circiut will not start up (always).

We do not recommend the use of a crystal like this, as we have experience that it doesn't always start up.

Will it work once? Sure. Will it works always, nope.

I suppose Lattice isn't large enough to worry...

Aust> Hi

Austin

Might be worth making the suggestion to your sister grouping of GPD of adding a dedicated oscillator crcuit to their range of products. Given a lot of micros do that already there would be some logic in adding such a circuit in the future to the low cost sector FPGA families.

John Adair Enterpo> Antti,

John, "been there, done that". XC3000 used to have a single-stage dedicated inverter, exactly for that purpose. It caused us a lot of support grief. Between 32 kHz and

This structure works with *any* kind of logic if you understand it has a pure analogic behaviour and you treat it as a sensitive analogic stuff (and not a digital one like most software guys do). The key for a stable oscillation are the crystal parameters and the value of the output capacitor connected to ground. A small one will increase the oscillation amplitude and decrease the stability. A very big one will increase the stability (and the start-up time) and decrease the amplitude below the gate thresold voltage. None of those situations are good. The input capacitor can be adjusted up to 50% without significant changes. If you plan a mass production, I suggest a variable capacitor of

Vasile

Well, no. Back when I was quite a bit younger, I tried to build a stable oscillator with a unused gate on a TTL 7414, with is an inverter with hysteresis. Tried all sorts of values of capacitors and resisters, and the best I was able to do was to usually generate the third harmonic. Sometimes the fifth, sometimes some other multiple of the crystal frequency, sometimes not a stable frequency, and sometimes even the frequency of the crystal. Switched to using a 7404, a plain inverter, and then making a stable oscillator was easy.

Did you put it into production and ship a million of them?

They used to make 74U04, U for unbuffered. It was intended for hacks like this.

I have submitted this idea (at least 1 DCM with pins for crystal) many years ago.

Antti

I assume Xilinx marketing is smart enough to analyze the tradeoffs.

I remember being grumpy that the 2 special IOBs on the 3000 series chips were slightly different. I don't remember the details, it was probably something like slightly slower or a few extra pF. It wasn't a big deal, at least most of the time, but it was one more thing you had to keep in mind.

Southbridge chips often contain the RTC and whatever it takes to drive a 32 KHz crystal. I haven't looked carefully, but I haven't seen one that includes the magic PLL clock generator stuff. That seems like a very tempting target for high volume cost sensitive applications so I assume there is a good reason they don't do it.

well, is that the same reason why Actel _INCLUDED_ oscillator in the Fusion :) ?

Antti

a few pennies? FPGA prices start from 2 USD, so extra 20 penny for the oscillator is over 10% of the FPGA cost.

there is magic thing called specification: if the oscillator would work reliable with 10 to 100MHz range then its sufficient to include that in the spec, and no-one would expect it to work with 32khz

adding 32khz support would require 1 extra config bit to select LP vs HS oscillator, very similar to fuse options by Atmel flash MCUs.

sure its additional engineering but.. MANY MANY MCU companies are including this option, and it is working and doable. I cant imaging it would not have been possible to test it without extra mask cost to xilinx, by addint 2 test pins during say V-4 initial testing. how many mask revisions was made? if the osc circuit would have been included xilinx would have plenty of time (mask revisions) to fine tune it. and in the case of failure those 2 magic pins would have "reserved" or GND marking in final datasheet.

simple. just a matter of decision.

Antti

Xilinx could buy such a circuit as IP and integrate it. The parts containing non-volatile configuration memory would benefit greatly and could potentially replace microcontrollers. A PLL would even be better and also reduces the range of crystal frequencies that need to be supported. 4MHz to 16MHz would be enough.

IIRC the '04 series are designed to be used as an oscillator. I remember some IC designer complaining that he had a hard time getting the re-design of a '04 right (usefull as an oscillator) in a fast process.

I'd be happy if Xilinx would simply provide a free running, loosely spec'd clock in the FPGAs that a designer could use for non-critical design. They could spec it as "it runs at some frequency between 5 and 30 MHz and will drift with temperature/ voltage, you can't set it, you can only use it." If they would let you use the Master Mode programming clock inside the design, I'd be happy. I don't care about the frequency, I just want a free running clock.

No crystal pads, no clock divider, just a ring oscillator within a reasonable frequency range.

John Providenza

Once upon a time I worked for a company that designed and manufactured motherboards and these sorts of oscillator were used very successfully.

John Adair Enterpoint Ltd.

Given the trouble getting a fast process to work in the `04 series, do you *seriously* believe that just "buying IP" would be more effective than having the extreme-silicon experts in a world-class organization such as Xilinx design the same things?

It seems that the "one size fits all" approach just doesn't do it.

The PLL is a reasonable idea, but might be best integrated with a glued-on MEMs resonator rather than a crystal, internal or external, for those few chips that could seriously benefit from a solid internal source. I liked the 78 ps input delay resolution on some high-end Xilinx chips (which are out of my own production price range) but these need a fixed training frequency to accompany them. What an excellent opportunity for an embedded oscillator!

Most systems I'm working in have a central timing scheme where the FPGA is nowhere near the center of the timing universe. If the more expensive chips (PLLs, trained timing) are the only ones that can afford the internal timing source, there's less probability that they'll be sourcing the timing for the rest of the design. And if you're paying tens of dollars for a chip, the 20 cents suggested earlier in the thread really is small potatoes.

For these higher-end chips, however, imagine the improvements in DLL jitter when the frequency is maintained by the lower-jitter internal timebase and the phase adjusted more smoothly by the external clock source feeding the DCM.

There are arguments for the timebase, but it's hard to strike an obvious cost/benefit tradeoff since the utilization would probably be way under the 50% point.

- John_H

No, but a commercial video display card in my S100 system that I still have uses the same scheme, and I seem to remember seeing the circuit in a data book in that timeframe. This scheme did seem to work, at least for the copies I used all the time, unlike the 7414, which did the most amusing other things, other than oscillate at the intended frequency. I don't recall seeing oscillators until the late 1970's.

CMOS gates came in both buffered and unbuffered versions, the unbuffered version for things like this. TTL gates gave you schematics. No buffer on this inverter, at least in the plain TTL version. Maybe on the 74F or

Isn't the marketplace wonderful? If Actel does what you need then use their parts.

KJ

LOL, I use the parts that meet the BOM budget, whatever brand their are ;) i'd prefer to use vendor X, but sometimes we cant do what we prefer

I think you are overrating Xilinx here. If they where experts on crystal oscillators, they would be selling crystal oscillators!

Probably, but I'm talking 'simple' circuits here. Imagine a microblaze with some dedicated logic to replace a microcontroller + some dedicated logic.