Hi Eveyone,
The specifications goes something like this :
The device core asserts reset to the device peripherals asynchronously and releases (deasserts) the reset synchronously after 4 clock periods
there are two possible implementations for the above spec which one is better :
signal reset_reg : std_logic_vector(3 downto 0);
p_reset_reg : process(clk,reset_async) begin if (reset_async = '0') then -- on async reset assertion reset the registers reset_reg '0');
elsif (clk'event and clk = '1') then
reset_reg(0)