Programming and debugging the Altera Cyclone family

No, you do not have to swap the connector as the ByteBlaster II supports multiple configuration modes.

The JTAG functionality is always available, but depending on how you set the MSEL(0,1) pins, you can programming the cyclone devices either in AS or PS modes.

I figured out that Byteblaster2 masters different modes. What I wasn't able to figure out yet was how to use the JTAG mode on the AS mode pins. Meaning (Fig3-7 configuration handbook / cyclone device handbook vol1) the AS mode uses Data, DCLK, nCs/nCSO, ASDI/ASDO, nConfig, Conf_Done, nCE. And JTAG uses TCK, TMS, TDI, TDO.

Preferably I'd program the EPCS1 & the Cyclone with JTAG, and use the same cable and connector for debugging too. That was possible with the ACEX family at least.

Rene

Yes, I agree entirely.

With the Actel proAsic devices ( flash based FPGA) not only do you do everything through the JTAG interface, but you can also add your own logic to the JTAG chain.

Thus, doing things like in-system programming are a stroll in the park.

Hmm, and what should I do with the Cyclone ? Have 2 connectors, one for the AS, doing the EPCS1 and the Cyclone and the other for the JTAG debugging ?

Rene

I think that you can also program the EPCS1 via the Cyclone chip itself but I do not know how off head.

This might work:

(1) Configure the FPGA through the JTAG port. (2) If you have an I/O connection between your logic in the Cyclone and a PC, download your configuration bitstream into the EPCS1 via your logic in the Cyclone. (3) Turn the power off then on. The Cyclone should boot from the EPCS1.

I don't think it's as easy as this.

There's an IP block AMSI which a NIOS processor can use to acesss/reconfigure an AS device, but this can't easily be accessed without the NIOS.

Details of how it's driven aren't published so it's probably not impossible to use, but not easy.

This seems a daft move by Altera as easy access to the AS device allowing in system up-dates would be a good marketing point.

Nial Stewart

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone based 'Easy PCI' eval board

All, There was a related thread on this topic, and I replied to it. I am cross posting the response to this thread as well:

The EPCS Serial Configuration Devices are programmed through a serial interface. While the device itself does not include JTAG, we have developed a method of programming it by JTAG by routing the data through the Cyclone device. In short:

1. The Cyclone FPGA is configured through JTAG.
2. The EPCS programming data is sent from the PC to the JTAG port of the Cyclone FPGA. This is done by Jam, so it can come from a PC, or from a Jam player running on an embedded microprocessor.
3. The logic in the FPGA captures data from the JTAG port of the Cyclone FPGA, reformats it to conform to the EPCS interface, and drives it to the EPCS device.

This capability (as a reference design with documentation) is available in beta form today, and will be included in a future version of Quartus II software. To get access to the beta version, please contact your FAE or Regional Support Center.

So, while the EPCS device is not directly connected to the JTAG chain, the device can be programmed by a JTAG controller by passing the data through the FPGA.

One final note - Altera also provides a tool called SRunner, which enables you to program the EPCS device directly from an embedded microprocessor. This is another solution to the question of how to program the EPCS device.

Greg Steinke snipped-for-privacy@altera.com

That's all very well if you can get to the board to plug in a JTAG connector, but what if you want the ability to allow remote updates.

I would like to be able to allow customers to update my Easy PCI board, over the PCI bus. This is achievable at the minute but it requires a NIOS core be permanently included in the design which uses a fair bit of the chip resource.

A small core allowing the Cyclone devices to easily access the ASMI interface would be a big bonus.

Nial

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone based 'Easy PCI' dev board.

I've done this using very little logic resources. It has a separate pci register (or even function) which has four writable bits (output enable, tck,tms, and tdi) and one readable bit (you can of course make a large buffer for efficiency). The device driver can then control this register and to drive all the jtag signals. You can then generate patterns to write to a jtag programmable configuration device, or control the scan chain of the fpga to generate a sequence to write data to a plain flash.

You might want to have a mux or similar to select the jtag input from your fpga (isp controller) or from the jtag connector on the board. It's also smart to have storage for two fpga configurations so you can revert to the fail safe one in case something goes wrong, i.e. a power loss during isp etc.

Petter

Altera has example designs demonstrating EPCS configuration using Nios in a Cyclone device. These designs come with the Nios Development Kit and include the software drivers. Mr. Stewart - I will contact you directly to provide those example files via email or ftp.

Sabrina Raza snipped-for-privacy@altera.com