Hello.
I am using Xilinx ISE Foundation 6.3i. I am trying to implement a sine lookup table (targeted at either SpartanIII or VirtexII) but I am getting a strange result when running functional simulation (testbench bellow) with Modelsim: instead of showing the first element from the array on the output after the first rising edge it shows the 12th. Everithing happens as if I had initialized the address counter with 11 instead of 0. I know I am making a basic mistake but I cannot figure out where or why.
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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sintab20 is Port ( i_Clk : in std_logic; i_En : in std_logic; i_Addr : in integer range 0 to 19; o_DataOut : out std_logic_vector(17 downto 0) ); end sintab20;
architecture Behavioral of sintab20 is subtype t_ROM_DATA is std_logic_vector(17 downto 0); type t_ROM_TYPE is array (natural range ) of t_ROM_DATA; constant k_SinTab20x1: t_ROM_TYPE(19 downto 0) := ( "000000000000000000", "001001111000110111", "010010110011110010", "011001111000110111", "011110011011110000", "011111111111111111", "011110011011110000", "011001111000110111", "010010110011110010", "001001111000110111", "000000000000000000", "110110000111001001", "101101001100001110", "100110000111001001", "100001100100010000", "100000000000000001", "100001100100010000", "100110000111001001", "101101001100001110", "110110000111001001" );
begin process (i_Clk) begin if rising_edge(i_Clk) then if (i_En = '1') then o_DataOut i_Clk, i_En => i_En, i_Addr => i_Addr, o_DataOut => o_DataOut );
-- *** Test Bench - User Defined Section *** i_En