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How do you add signals within your VHDL architechture using Xilinx 7.1 ISE Simulator?

Brad Smallridge aivision dot com

Reply to
Brad Smallridge
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If you mean how to add signals to the simulation graphic, just open the whole tree of the UUT on your Sim Hierarchy tab (on the left side, beside Process View), choose the signal you need, drag and drop it inside the simulation graphic and you're done. Then re-run the simulation to see their behaviour. Marco

Reply to
Marco

I see my inputs and outputs, but no internal signals.

Reply to
Brad Smallridge

OK, I have it now. Enter the testbed waveform, run the simulation, open up the UUT, drag and drop, run the restart. Thanks.

Reply to
Brad Smallridge

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