I2C timing problem

hi! i am developing i2c master in FPGA. suppose ia m transmitting 1. i have doubt whether data transition should be at mid edge of scl when it is low or at the falling edge as in the below waveform.

scl -------------- ---------------------- | | | / here | / or | | ------------------ ---------------------------- |------------------- | here | SDA ---------------------- |------------------------------------

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The timing spec you want in the I2C bus specification is called tHD (data hold time after falling edge of SCL). Minimum spec is

0 ns (like your first picture) maximum depends on whether you are driving SCL or not. For a master just be sure to meet the setup time to the next rising edge of SCL. For a slave, you need to observe the maximum for the clock rate used, because you can only control the rising edge of SCL if you implement clock stretching. For 100 KHz devices, the max is 3.45 uS. for 400 KHz it is 900 nS.

The best practice is usually to sense that the SCL line has fallen using feedback from the pin, and then allowing the data to change.

Regards, Gabor

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