Hi.. I am trying to implement the Rocket I/O interface on the Xilinx Virtex-II Pro FF672 kit from Avnet. The reference design is EDK based and uses the powerPC. I would like to know the procedure for implementing Rocket I/O on this board using the logic fabric ( I presume that the power PC just slows down everything and moreover the logic fabric would be better suited for my application). I am using the Fibre channel for connection. Aurora is not an option here due to limited licenses. So one option I am currently exploring is the Architecture wizard which gives me a HDL interface for the Rocket I/O. But I am not sure about exactly defining the .ucf file for the different pins. If anybody has a pointer to this problem or some sort of info on the pinouts/ucf file, please pass it on. Thanks in advance, Vivek
- posted
17 years ago