Hi!
I'm doing the Modular Design Flow for Xilinx Virtex2 Pro (XC2VP7) device. I'm having problems getting all my BRAM's for my module. Since I do modular design I can only use one RANGE constraint, so I always get a rectangular AREA_GROUP RANGE. (Answer Record # 16423)
AREA_GROUP "AG_system_0" RANGE = RAMB16_X0Y0:RAMB16_X4Y8; works fine, but I'm missing the BRAM located at X0Y9.
AREA_GROUP "AG_system_0" RANGE = RAMB16_X0Y0:RAMB16_X4Y9; gives me an map error:
"ERROR:MapHelpers:151 - Error while processing the area group range. Unable to create a LOC object using the constraint RAMB16_X0Y0:RAMB16_X4Y9 attached to area group AG_system0. One or more ranges contain syntax error or illegal site. Please modify the constraint."
OK. I must not use forbidden BRAMs at X1Y9:X4Y9, but why is there no problem with forbidden BRAMs at X1Y0:X4Y0
Is there a way to get the missing BRAM for my design?
Thanks in advance Andreas snipped-for-privacy@lowtexx.de