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Global Clocks in Xilinx ISE

Hi,

I'm programming on a Spartan-II in ISE. I have a few questions about the clk signals and .ucf files.

I have assigned my two clock signals PCI_CLK and DHSM_CLK to GCLKBUF0 and GCLKBUF1 respectively. However, when I compile it gives an error that PCI_RST should be assigned to a GCLK. Is this happening because a lot of logic is dependent on the RST? Also when I look at the clock report in Xilinx I see:

+---------------------+--------------+------+------+------------ +-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------ +-------------+ | DHSM_CLK_BUFGP | GCLKBUF0| No | 544 | 0.338 | 0.472 | +---------------------+--------------+------+------+------------ +-------------+ | DHSM_RST_BUFGP | GCLKBUF3| No | 231 | 0.091 | 0.523 | +---------------------+--------------+------+------+------------ +-------------+ | PCI_CLK_BUFGP | GCLKBUF1| No | 204 | 0.353 | 0.487 | +---------------------+--------------+------+------+------------ +-------------+ | wf_data_in_flag | GCLKBUF2| No | 12 | 0.077 | 0.506 | +---------------------+--------------+------+------+------------ +-------------+ | d1/c1/mean8_stored | Local| | 2 | 0.000 | 0.908 | +---------------------+--------------+------+------+------------ +-------------+ | d1/c1/rng_stored | Local| | 2 | 0.000 | 0.728 | +---------------------+--------------+------+------+------------ +-------------+ | d1/c1/_not0004 | Local| | 5 | 0.000 | 2.659 | +---------------------+--------------+------+------+------------ +-------------+ | d1/c1/off_stored | Local| | 2 | 0.000 | 0.728 | +---------------------+--------------+------+------+------------ +-------------+

but off_stored, rng_stored, mean8_stored, and wf_data_in_flag are just wires in my design that are intended as flags. Where does _not0004 come from and why is it assuming that all of these things are clocks??

Thanks, Ian

Reply to
idp2
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Hello, I had something similar happening (am using spartan II as well), inexplicable, and it just stopped being a problem after upgrading (from

8.2) to 9.1. I'm a newbie so the hows and whys of what is going on I don't know. Maybe upgrade if you haven't already?

Good luck! Jesse

idp2 wrote:

Reply to
jesse lackey

Thanks for the advice...unfortunately the upgrade did not do the trick for me :(

Ian

Reply to
idp2

I'm guessing that your HDL is not matching a standard sync or async reset flipflop and so RST ends up looking like a clk. For example, if you say:

always @(posedge rst) foo

Reply to
Ben Jackson

matching a standard sync or async

Reply to
idp2

If the always block is not a clocked block, i.e. always @* it is possible to create latches. In the FPGA fabric the gate input of a latch uses the clock routing. Did you check if there were any transparent latches created in synthesis?

Reply to
Gabor

What I was doing wrong was assigning wires to 0 upon rst. This in turn caused rst to be viewed as a global clock. Thanks for all of your help.

Ian

Reply to
idp2

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