Global Clocks in Xilinx ISE

Hi,

I'm programming on a Spartan-II in ISE. I have a few questions about the clk signals and .ucf files.

I have assigned my two clock signals PCI_CLK and DHSM_CLK to GCLKBUF0 and GCLKBUF1 respectively. However, when I compile it gives an error that PCI_RST should be assigned to a GCLK. Is this happening because a lot of logic is dependent on the RST? Also when I look at the clock report in Xilinx I see:

+---------------------+--------------+------+------+------------
+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------
+-------------+ | DHSM_CLK_BUFGP | GCLKBUF0| No | 544 | 0.338 |
0.472 |
+---------------------+--------------+------+------+------------
+-------------+ | DHSM_RST_BUFGP | GCLKBUF3| No | 231 | 0.091 |
0.523 |
+---------------------+--------------+------+------+------------
+-------------+ | PCI_CLK_BUFGP | GCLKBUF1| No | 204 | 0.353 |
0.487 |
+---------------------+--------------+------+------+------------
+-------------+ | wf_data_in_flag | GCLKBUF2| No | 12 | 0.077 |
0.506 |
+---------------------+--------------+------+------+------------
+-------------+ | d1/c1/mean8_stored | Local| | 2 | 0.000 |
0.908 |
+---------------------+--------------+------+------+------------
+-------------+ | d1/c1/rng_stored | Local| | 2 | 0.000 |
0.728 |
+---------------------+--------------+------+------+------------
+-------------+ | d1/c1/_not0004 | Local| | 5 | 0.000 |
2.659 |
+---------------------+--------------+------+------+------------
+-------------+ | d1/c1/off_stored | Local| | 2 | 0.000 |
0.728 |
+---------------------+--------------+------+------+------------
+-------------+

but off_stored, rng_stored, mean8_stored, and wf_data_in_flag are just wires in my design that are intended as flags. Where does _not0004 come from and why is it assuming that all of these things are clocks??

Thanks, Ian