Webpack 9.1 problems with Impact on parallel cable

After upgrading to Webpack 9.1 (and then directly to service pack 1) on a Windows XP machine connected to a Diligent Spartan 3 Stater Kit via a parallel cable I am no longer able to program the FPGA. Impact complains that "done did not go high" even though everything else (checking ID and such and the uploading itself) seems to be working fine.

The board runs the example in its Flash just fine but is dead after I try to upload anything to it. I have some older .bit files which used to work, so the problem doesn't seem to be that 9.1 is generating a bad bitstream (my initial guess since it was so slow and actually crashed once). Since I had to uninstall the previous version (8.2, I think) before I could install this one I can't check using the old Impact.

The computer is a Dell OptiPlex GX1.

On a totally different subject, Webpack 7 had compiled the System09 example (an implementation of a 6809 computer) just fine for the Spartan 3 200 while Webpack 8 tried to allocate 13 block rams and failed. Webpack 9 only wants 5 block rams for the same design. I found this much variation a bit suprising, though I suppose this is due to differences in the default settings.

-- Jecel

Reply to
Jecel
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I've tryed ISE9.1 SP1.. and it crash!!! Then I come back with ISE8.2... and I can't open my old projects!!!

Reply to
Quesito

This is because they changed the format for the project file again. If you start up ISE9.1, it loads your most recent project by default and automatically converts it to the new format, which cannot be read by ISE8.

There's a yellow leaflet in the box to warn you about this. Of course, if you use WebPack, there's no box... :)

--
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...
Reply to
Sean Durkin

I think the old version was saved as a .zip somewhere. So it should be possible to recover.

And the dialog box asks permission before converting the project. It also asks permission to save the old version (I think) and tells you where it put it, but I didn't pay attention to that. I can easily load that particular project from the Internet again if I need to, so I wasn't worried about that.

Reply to
Jecel

Your projects should be in some sort of source-code control system, which will easily allow you to go back to any arbitrary version.

-a

Reply to
Andy Peters

Not everyone knows what a source control system is. As an example, I use this one:

formatting link

As Francesco seems to be on windows, I'd also suggest this:

formatting link

If Francesco was using subversion, then he would recover after:

svn revert projectname.ise

Or a couple of mouse clicks using tortoisesvn.

Would have been much easier and faster than posting to comp.arch.fpga.

Hope that helps.

--
Phil Hays (Xilinx, but posting for myself)
Reply to
Phil Hays

I don't think is so simple Phil... I did backed up my project before use 9.1! Yes ISE 9.1 for default open your old project but also ask you "This project was made with an older version of ISE do you want to open?" (or a similar message) And I pressed "NO"... Maybe ISE 9.1 said Did you pressed NO? I don't care I'll open anyway.. I'm not the only person in my company having this sort of problem and we are very sceptic on 9.1.. and waiting now for the SP2!

I belieave that you guy at Xilinx are excelent engineer... but this sort of negative feedback must be taken seriously from you. It is actually the first time in 6 years that I'm starting to think to swtitch to Altera!

Francesco

Reply to
Francesco

Francesco,

I'm a little person at Xilinx. I've designed using Xilinx FPGAs for about

15 years, and have worked for Xilinx for less than a year. I have much more experience giving feedback than getting feedback. As a long time user of Xilinx's software and FPGAs, I have given feedback to Xilinx in many ways and on many topics. Xilinx, as a whole, has listened well and has taken this feedback seriously. I don't think that I was listening well to your feedback.

Thinking as a long time user of FPGAs, I replied to Andy Peters comment to suggest a specific source control program. Bad things happen. Not only can software behave badly, and not only Xilinx's software, but also I make mistakes and need to recover from them. A source control program allows for quick and graceful recovery from many of these problems. I have been suggesting use of source control programs (cvs, svn and many others) for years.

I used your problem as an example of why using a source control program would be a good habit. This was rude of me, I'll try to listen better in the future, please forgive me.

--
Phil Hays (Xilinx, as usual, writing for myself)
Reply to
Phil Hays

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