Hi, When i use Synplify to synthesis my VHDL design and then i enter the EDIF result file to ISE 6.1 softare and then i can creat area constraint without any troubles. Now if i enter directly my VHDL design to ISE and then synthesis it, when i open "creat area constraint" window, in the design broser window it doesnt shows the logic of my design that i need to place manualy (the folder existe but is empty) it shows only I/o Pins and Global logic (these folders are note empty). How to fixe this ? any idea?.
Thanks for any help.