Partial Reconfig - PAR fails with ISE 6.1 SP3

Hello, Ian:

I saw you mentioned the Spartan-2 bus macro, could you exchange it with me? I am willing to trade for it with a complete partial reconfig design (vertex-2)...that was the tutorial I did, though...My email address is snipped-for-privacy@hotmail.com...

Best Regards, Kelvin

I don't know if you saw the thread about this a few days ago, I had some similar inexplicable problems with the tools producing invalid NCDs, that would crash the FPGAeditor and bitgen tools.

The bottom line seems to be that there are still a lot of issues to be worked out! I'm sorry I don't have any concrete suggestions for your problem, but it does make me wonder...

Would there be interest in a partial reconfiguration research mailing list? Or, is there already such a thing?

Our department has a list-server configured and ready for use (I currently run the microblaze uclinux list on it). I'd be happy to setup and maintain such a list, if there was interest.

Regards,

John

Kelvin, bus macro sent via Email. Anybody else need this part just ask!!

John, I'm glad it's not just me!

Also, thanks to John, the partial reconfig list is now active at

just one thought however, does it have to be restriced to Xilinx devices??

Cheers All, Ian.

Thanks for the advertising Ian :) Anyone wanting to join can send an email to snipped-for-privacy@itee.uq.edu.au, with the *body text*

subscribe partial-reconfig

Not at all - I just wonder how much of the detailed implementation / tool flow discussion would be relevant between brands A & X.

I'm happy to broaden the charter to partial and dynamic reconfiguration generally.

Regards,

John