I have a simple partial reconfig design. Under ISE6 SP2 it is only routable using fpga editor, command line PAR fails with the message 'abnormal program termination'. Not a big problem as fpga editor does the job!
But after installing SP3, command line PAR and fpga editor fail reporting the design is unroutable. The problem is confirmed as being SP3 as I have now uninstalled it and the design routes OK.
If anyone is having similar problems routing a design you may want to do the same.
I would also like to thank Kamal Patel at Xilinx for his help and for creating a Spartan 2 bus macro, amazing service!! Cheers :)