ise 10.1 (Linux) contraints problem

problem.

VHDL

were

again,

to

clear

Under Project menu, "Cleanup Project Files" might be what you are after. Ensure that the [name].restore file is deleted, too.

--------------------------------------- Posted through

leave the GUI and use scripts, it never causes these problems!

/michael

Great, thanks! That option was staring me in the face. All is working now.

Jon

Well, I'll have to learn how to do this.

I did use a command line to run promgen, as running it from the GUI crashes.

Jon

es.

Jon,

When you read the documentation for using the command line mode, you will find that there are a number of files that are included implicitly if found. Most likely it was one of those files (.pcf is the most likely culprit) that was causing your problem.

"Real engineers don't use GUIs", RK

To synth define PROJECT or replace with project name xst -ifn ${PROJECT}.xst -ofn ${PROJECT}.log

You could use xflow to run the flow for P&R xflow -p partname ${PROJECT}

There are probably even better ways that a are compatible with the GUI ising tcl I assume but I have not digged in to that, I am to old...or maybe not ;)

And then bitgen like you have done with promgen

You might need some config for bitgen

/michael

OK, well I can probably dig the syntax out of the log files. I had no idea it was that simple!

The Windows-fashioned text editor in ise is pretty awful, I usually use emacs.

I DO like the simulator, though. MUCH easier to hop around in the hierarchy and bring up signals from various inner components of the design than Modelsim. And, it automatically saves the signals on the screen for next time.

The promgen command line I got from a Xilinx article puts out the reverse bit ordering, so it wouldn't load. I'll have to figure out what option sets it for the other ordering. But, after I did the cleanup, the prom file formatter works from the gui. I need to find out what I'm doing wrong that fouls up the management of vhdl files. I put the files into a directory and edited them for the first cut there before setting up an ide project and adding the files to the project. This left several versions of files with the same name in the various levels of the directory, and I think that is what started this mess.

I think working both outside ide and inside it is most of the cause of the problem.

Jon

There have been an article in Xcell journal on how to use Xilinx tools in command-line mode, if anybody is interested:

Thanks, Evgeni

Hi Jon, read the excelent article pointed out but outputlogic and go scripting. Next move is go linux perhaps starting on a Virtualbox installation on top of your Windows.

Good to hear that you use Emacs, have you installed the VHDL and Verilog extensions to emacs?

Well, that article is for 12.1, there might be a few changes to make it work with 10.1, but I do appreciate that article.

I HAVE gone Linux, and am doing all new projects there, but I have some older projects to maintain, some even using classic 5V Spartan, so I can't completely abandon the ancient Windows stuff. The problem I was having was on the Linux 10.1 system, (as I even said in my subject line.) Yes, it has the VHDL language templates, but I'm not sure I really like them. Maybe I need to learn how to use them better.

I use Linux native, and run Windows as a guest OS under VMware.

Jon