ISE guide mode broken?

Has anyone encountered this problem using Xilinx ISE 6.x ?

1. Implement a design so that it meets all timing constraints.
2. Run Backannotate to lock the pins down in the ucf file.
3. Set the PAR'd ncd file as the guide file for MAP and PAR.
4. Reimplement the design and have the timings change enough that constraints are not met. No changes done other than running backannotate to add the pin locs to the ucf file.