Open Collector Circuit - How to Simulate?

Actually it should. An open collector (which would be for almost all fpgas) configuration can be modeled with a tri-state output which can be driven low or tri-stated, not driven-high. You should be able to use a regular tri-state bi-directional io to do what you need.

Try this:

module od_io(pad, in, oeb); inout pad; output in; input oeb;

wire pad = oeb ? 1'bz : 1'b0; wire in = pad;

endmodule

this should map to a bi-dir io or you can instantiate one from your device's library.

You didn't say what you are modeling in. Assuming you are using VHDL or Verilog, a tri-state bus is modeled using STD_LOGIC. A tri-state open collector driver will drive either a '0' or an 'X'. Any of these drivers can overdrive the 'X' of another when they drive a '0' which is a "strong" drive. If you want to model a pullup resistor, drive the net with a constant 'H' from another source. This is a "weak" high and will overdrive the 'X', but be overdriven by the '0'. In most logic functions, the 'H' will be treated the same as a '1'. Or you may have to convert to '0', '1' before using this bus as an input.

And make sure you have a pull up resistor external.