PC Core AD(x) I/O Enable?

I notice that the Xilinx PCI32 core for Spartan 3 does not map the tristate enable FF's for the AD(x) lines to IOB's. Is there a good reason for this? The only adantage I can see for this is to try and force the AD(x) data FF's to contain the newest data before the IOB's are enabled.

Anthony.

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Anthony Ellis
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Another reason may be to stagger the enable into four groups to control the amount of simulateous switching outputs?

Reply to
Anthony Ellis

Hi Anthony,

The reason tri-state enable FFs are not included in AD[31:0], C/BE#[3:0], PAR's IOB is for timing reason. Xilinx (and many FPGA-based PCI IP cores) LogiCORE PCI is taking advantage of Address Stepping (Mentioned in PCI Specification) allowed by PCI Specification. Address Stepping allows the device to turn on data bus signals ( AD[31:0], C/BE#[3:0], PAR) multiple cycles (Usually one cycle to minimize performance hit.) before it needs to be turned on, giving very good timing margin. If Address Stepping wasn't allowed, yes, those tri-state enable FFs will have to be included in the IOBs, and will also have to rely on unregistered PCI control signals to turn on the data bus signals, making it very difficult to get the PCI IP core to meet PCI's setup time. (Particularly 66MHz PCI where the setup time is only 3ns.)

Kevin Brace

Anth> I notice that the Xilinx PCI32 core for Spartan 3 does not map the tristate

enable FF's for the AD(x) lines to IOB's. Is there a good reason for this? The only adantage I can see for this is to try and force the AD(x) data FF's to contain the newest data before the IOB's are enabled.

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Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available 
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Reply to
Kevin Brace

Hi Kevin,

I can't figure your explanation. Even if you wnated to step (in clock cycles) the IO enable could still be in the IOB! Using an internal FF, with defined placement and routing, gives control of scew within the same cycle - if you wanted it!

Anthony.

Reply to
Anthony Ellis

Hi Anthony,

Data bus signals' tri-state FF not being included in an IOB is for timing reasons. Even when Address Stepping is used, those FFs still do rely on several unregistered signals, and when larger devices are used, the unregistered signals (i.e., FRAME#, IRDY#, etc.) will have to travel longer distance, thus making harder to meet the PCI's stringent setup time requirement. (3ns for 66MHz PCI and 7ns for 33MHz PCI.) Instead, by not including a tri-state FF in IOBs, it allows the tri-state FFs to be placed near the unregistered signals, making it easier to meet setup time. Once those unregistered signals go through LUTs, and get captured by a FF, they become registered, and once registered, the registered signal has much more timing margin. (15ns for 66MHz PCI and 30ns for 33MHz PCI.)

Kevin Brace

Anth> Hi Kevin,

the IO enable could still be in the IOB! Using an internal FF, with defined placement and routing, gives control of scew within the same cycle - if you wanted it!

--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available 
 Click to see the full signature
Reply to
Kevin Brace

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