What's the way to do this? It's common for me to run into situations where I have a bus or bus pin, and I need to connect the same net to different lines on the bus. Another common one is I have 2 busses, both of which have a line that should connect to a single net. The documentation doesn't seem to give any hints. Thanks for any input.
-- Alex Rast ad.rast.7@nwnotlink.NOSPAM.com
A)
B)
While I have not used ECS, the way we did this in previous schematic systems was to pass the source single through multiple "BUF" symbols.
Look in the libraries guide:
Libraries Guide -> Design Elements -> BUF
A) sourcenet -> BUF -> dest_bus_[2] sourcenet -> BUF -> dest_bus_[3]
B) SourceBusBit_[3] -> BUF -> DestBusBit_[6]
The BUF is a primitive that uses no logic resources. It is used to alias one signal name to another, and is trimmed out during the P&R process
Philip
=================== Philip Freidin snipped-for-privacy@fliptronics.com Host for
What does "connect the same net to different lines on the bus" mean?
Do you want a mux or tri-state driver, to read a status bit when a particular register is selected? Or do you want a solid connection
100% of the time?If you want a hard connection, then physically, you are merging several nets into one. That seems a bit strange if two of them are part of the same bus.
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It seems stupidly cumbersome to have to do this. Since I'm not thrilled (read "mistrust the software" about relying on something to be trimmed out during P&R - incidentally, why do no S/W packages seem to want to allow an easy way for you to define P&R manually, when P&R is the one thing that a computer does the least well - so I created the following general-purpose VHDL "component"
entity ConnectLine2Bus is Generic (BusWidth : integer := 8); Port ( InputSignal : in std_logic; OutputBus : out std_logic_vector((Buswidth-1) downto 0)); end ConnectLine2Bus;
architecture StraightThrough of ConnectLine2Bus is
signal ConnectInt : std_logic;
begin
ConnectInt
One can also do this by reference using a "cat bus". For example, suppose you have the named signals, A, B, and C. You can create an 8-bit bus by naming it: "A,B,B,C,A,A,A,C" (remove quotes, can't remember if you might need parenthesis around the whole mess)
Philip Freid> >
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