Dear everyone We are doing DDR interface design with the Xilinx Virtex-4. Actually, it's kind of straight forward, I just want to use MIG 1.5 to generate a module that we want to use. Is that necessary to use Modsim to simulate the design? Can we just use Xilinx ISE to do that job? Since this will cost extra and we are in tight budget. We don't have too much experiences on that. Anyone did that?
Thanks, C.
No, it's not, however it might be useful to do some signal integrity simulation instead...
/Mikhail
I have another question regarding this topic?
Is it possible to use cadence NCSIM? I tried and it runs, no crypted library problems or anything still I get loads of bit error out of bounds faults and the DDR model does not work. I can write data but cannot read it back. Any ideas?
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