questions on Xilinx Virtex-4 to DDR SDRAM module

I have a few questions in the design of a connection from Xilinx Virtex-4 to DDR SDRAM 200-pin SO-DIMM module

First is if pull-up (to Vtt) termination of clock lines (on the module end) is needed. These clocks are SSTL differential signals in pair and many datasheets show the cross 120 ohm termination on the module. It means they do not need Rt 50-ohm to Vtt termination as other SSTL signals (data, address and control) do. but I can not find explicit description or statement on this. Can anybody confirm it?

Second question is how to configure the pins on Virtex-4. They are all SSTL2-II or DIFF_SSTL2_II. Do I need to set DCI? I am not sure. I tried Xilinx mig1.21. It gave me straight SSTL2-II/DIFF_SSTL2_II without DCI. Do I need Rt 50-ohm to Vtt termination near those FPGA pins?

Thanks for your help in advance.

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wwqiao
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