Verilog Encounted Errors

Hi to all,

I'm writing a short program using verilog at the moment ,and I encountered 4 errors of the same kind (a net is not a legal value in this context). I've been tring to edit the program but i still get the same errors... I need help urgently .Can someone explain the errors?

Thanks a lot!

Below is my program and I have indicated where the 4 errors (a net is not a legal value in this context) the compiler pointed to.


`timescale 1ns/1ps

module encoder(eingated, clr, clk, inhibit, keydet, eout); input [3:0]eingated; input clr, clk, inhibit ,keydet; output [3:0]eout; reg [3:0]eout;

parameter idle = 1'b0, keypressed = 1'b1; reg [1:0] cur_state, next_state;

always @(posedge clk or negedge clr) begin if(clr==0) cur_state = idle; else cur_state = next_state; end

always@(cur_state or eingated) begin case(cur_state) idle : if (eingated == 4'b1110 || eingated == 4'b1101 || eingated == 4'b1011 || eingated == 4'b0111) begin keydet = 1'b1;

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inside an always process you can assign only reg not nets. An input is a net unless you declare it also as a reg. Review Verilog 101 :)



Tullio Grassi

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Tullio Grassi

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