Hello all, I am generating the clock of frequency 548KHz from an input clock of
73.728MHz. I am using the Direct digital frequency synthesis DDFS technique fromNormal exit
*********************************************************************** Here is the code of my program: *********************************************************************** // Thanks to Jonathan Bromley for his valuable suggestions for the code. `timescale 1ns/1ps module fulladd28(out,clock,reset); parameter a=28'd1995207; parameter w = 28; // bit width of phase accumulator output out; input clock, reset; reg [w-1:0] sum; always @(posedge clock or posedge reset) if(reset) sum