DDFS technique problem in generating a few clocks

Hello all, I am generating the clock of frequency 548KHz from an input clock of

73.728MHz. I am using the Direct digital frequency synthesis DDFS technique from
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But I am getting the wrong output as; ************************************************* Running... 929 929.134 t=0.000000 929.134period=929.134000 929.134t=929.134000 freq=1076271.022264 HZ 2747 2746.71 t=929.134000 2746.71period=1817.576000 2746.71t=2746.710000 freq=550183.321083 HZ 4578 4577.85 t=2746.710000 4577.85period=1831.140000 4577.85t=4577.850000 freq=546107.889075 HZ Exiting VeriLogger Pro at simulation time 10000000 0 Errors, 0 Warnings Compile time = 0.00000, Load time = 0.04700, Execution time = 0.04700

Normal exit

*********************************************************************** Here is the code of my program: *********************************************************************** // Thanks to Jonathan Bromley for his valuable suggestions for the code. `timescale 1ns/1ps module fulladd28(out,clock,reset); parameter a=28'd1995207; parameter w = 28; // bit width of phase accumulator output out; input clock, reset; reg [w-1:0] sum; always @(posedge clock or posedge reset) if(reset) sum
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Here is a simple suggestion: Your output frequency divided by your accumulator clock frequency is

0.0074327256 as displayed on my cheap calculator. Just convert this decimal value into a binary fraction, and that gives you the inputs to your accumulator. You can make the accumulator more than 20 bits long to increase the average frequency accuracy, but you will still get a jitter of one ~73 MHz clock period, which is roughly 0.7% of your output period. If you absolutely need less jitter, there are tricks (like multiple accumulators), but they get complicated and/or expensive.

Good luck. Peter Alfke ===========================

Atif wrote:

Reply to
Peter Alfke

hi peter,

I went through one of the application note(xl31_32.pdf) of xilinx on DDFS. he gives the eq Fout=Fclk * N/2 power k.Is there any effective method of selecting the value of N and k or is it trial and error.

Thanks in advance.

rgds, praveen

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You can determine k from the required frequency accuracy, as the output frequency is quantized in steps of Fclk / 2^k

E.g. Fclk is 73.728 MHz, k of 20 bits gives a step size of 70.3125Hz.

N determines the output frequency, as above.

Using some primary school algebra, we can work out an expression for the ideal value of N as:

Nideal = (Fout / Fclk) * 2^k

now round Nideal to an integer to give N.

E.g. Fclk is 73.728 MHz, Fout is 548kHz

k N Error

18 1948 -228.1ppm 19 3897 +28.5ppm 20 7794 +28.5ppm 21 15588 +28.5ppm 22 31175 -3.6ppm 23 62350 -3.6ppm 24 124700 -3.6ppm 25 249401 +0.4ppm 26 498802 +0.4ppm 27 997604 +0.4ppm 28 1995207 -0.06ppm ...

Regards, Allan.

Reply to
Allan Herriman

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