Hello, I have a question regarding DDR2 memory controller. In a read operation from DDR2 based on strobe, do one need to shift the strobe by 90' in order to capture the valid data, or is there any pther way for it ?
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The optimal phase shift will depend on the 2-way track delay between the Controller IC (e.g. your FPGA) and the SDRAM (clock out, data back).
Taking the DDR2 SDRAM Controllers generated by the Xilinx MIG tool as an example, they go through a training period working out the best phase shift relative to the FPGA-internal clock to sample the read data.
Alternatively, you could route the SDRAM clock back to the FPGA, and use that.
Neither is easy. Therefore use your FPGA vendor's IP if at all possible.
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