Is it not recommended to use the ISERDES in the Virtex-5 to perform strobe-based read capture from a DDR2 SRAM (not QDR) part? I'm routing my echo clock (CQ) into the FPGA through an IODELAY component, then BUFIOs, and then straight to the 18 DQ pins (ISERDES blocks) using local clock routing. I'm seeing random bit errors that I attribute to the read capture path. Based on the errors, I think it might have something to do with the CQ and CLK phase relationship, but I'm not sure. I'm calibrating the read path using the 3 stage technique described in XAPP858. I'm seeing some good valid windows delaying my individual DQ data variably. I'm not getting any errors when I delay the DQ and CQ in lock-step in phase 2.
I just looked at the RTL vhdl code generated by the MIG for a DDR2 SDRAM controller and found that the ISERDES aren't used. Instead, the data is clocked in by an IDDR flop, and then directly into carefully placed fabric flip-flops (using a phenomenal number of directed routing constraint attributes).
Could someone explain to me when using ISERDES for strobe-based read capture is applicable, versus using the IDDR + hand-placed fabric flip- flops?
Thank you.
-Petersen Curt