I have a problem and I need a clean solution: I created an OPB peipheral which includes AsyncFIFO (created with FIFO generator). I have included the edn (tried also with ngc) in bbd file and a VHDL wrapper (original, created by CoreGen). During build I get the following error: ERROR:NgdBuild:604 - logical block 'imam_0/imam_0/FIFO' with type 'async_fifo' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'async_fifo' is not supported in target 'virtex4'. I did managed to overcome the problem somehow several times by changing bbd and netlist filenames, but the problem comes to the surface every time I clean all the EDK project files.