... solve the following?
A Xilinx DCM generates clk and clk2x For each coinciding edge there should be generated a clock enable for the higher freq. clock (which is a toggle FF with the right phase)
Which solution have you used?
Homann
-- Magnus Homann, M.Sc. CS & E homann@homann_REM_.se
That is a great question. It seems to me that the DCM really needs an output, in the clk2x domain, that tells you which cycles are aligned with the 1x clock. It's very often that I have to transfer data from the 1x domain to the 2x domain and then it's very useful to know this so I can maximize setup time.
The way I do it is to have a 'T' flop (that toggles every cycle) in the 1x clock domain. This gets sampled in the 2x domain, and an edge detector in the fast domain determines which 2x cycles are aligned with the 1x cycles.
-Kevin
How much skew do you tolerate with that design?
My idea was to have two FFs that was clocked by the falling and rising edge of the clk2x.
clk2x------------ | ______ | ______ |-o|> | |--|> | | | | | clk-----|D Q|-----|D Q|---- clk_ce | | | | ------ ------
If duty cycles are 50/50 this should tolerate quite som skew, right?
Takes two slices.
Hmm, if you use clk90 and ckl2x, you could sample on rising edge of clk2x, and then you only need one FF.
Objections anyone?
Homann
-- Magnus Homann, M.Sc. CS & E snipped-for-privacy@dtek.chalmers.se
The diagram above might work, but it's a little less tolerant. If you are resyncing the 'T' flop in the 2x domain, you are more certain that you will meet setup and hold times because the output of the flop will change after the clock edge. With the diagram you have, the flops must tolerate zero hold times and you hope that differences in routing are not going to cause hold setup time violations.
The clk90 method might be better.
-Kevin
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