What is wrong with my DCM experiment? How come the testbench won't simulate DCM1.

Hi, there:

What is wrong with my DCM experiment? How come the testbench won't simulate DCM1, the clk1 is low. DCM0 is working fine though.

Thanks. Kelvin

`include "D:/dsp/src/defines.v"

module dcm_clkman( clock_in, clock_2_out, clock_3_out, clock_with_ps_out, reset ); input clock_in; output clock_2_out; output clock_3_out; output clock_with_ps_out; output reset;

wire low; wire high; wire dcm0_locked; wire dcm1_locked; wire reset; wire clk0; wire clk1; assign low = 1'b0; assign high = 1'b1; assign reset = ~ (dcm0_locked & dcm1_locked);

wire clock_2_out; wire clock_3_out;

assign clock_2_out = clk0; assign clock_3_out = clk1;

IBUFG CLOCK_IN ( .I(clock_in), .O(clock) );

DCM DCM0 ( .CLKFB(clock_out), .CLKIN(clock), .DSSEN(low), .PSCLK(low), .PSEN(low), .PSINCDEC(low), .RST(low), .CLK0(), .CLK90(), .CLK180(), .CLK270(), .CLK2X(clk0), .CLK2X180(), .CLKDV(), .CLKFX(), .CLKFX180(), .LOCKED(dcm0_locked), .PSDONE(), .STATUS() ); /* synthesis xc_props="DLL_FREQUENCY_MODE = LOW,DUTY_CYCLE_CORRECTION = TRUE,STARTUP_WAIT = TRUE,DFS_FREQUENCY_MODE = LOW,CLKFX_DIVIDE = 1,CLKFX_MULTIPLY = 1,CLK_FEEDBACK = 1X,CLKOUT_PHASE_SHIFT = NONE,PHASE_SHIFT = 0" */ // Do not insert any carriage return between the // lines above. BUFG CLK_BUF0( .O(clock_out), .I(clk0) );

DCM DCM1 ( .CLKFB(clock_with_ps_out), // .CLKFB(), .CLKIN(clock), .DSSEN(low), .PSCLK(low), .PSEN(low), .PSINCDEC(low), .RST(low), .CLK0(), .CLK90(), .CLK180(), .CLK270(), .CLK2X(), .CLK2X180(), .CLKDV(), .CLKFX(clk1), .CLKFX180(), .LOCKED(dcm1_locked), .PSDONE(), .STATUS() );

/*synthesis xc_props="DLL_FREQUENCY_MODE =LOW,DUTY_CYCLE_CORRECTION = TRUE,STARTUP_WAIT = TRUE,DFS_FREQUENCY_MODE = LOW,CLKFX_DIVIDE =

1,CLKFX_MULTIPLY = 1,CLK_FEEDBACK = 1X,CLKOUT_PHASE_SHIFT = FIXED,PHASE_SHIFT = 0" */ //Do not insert any carriage return between the //lines above. BUFG CLK_BUF1( .O(clock_with_ps_out), .I(clk1) ); //The following Verilog code is for simulation only //synthesis translate_off defparam DCM0.DLL_FREQUENCY_MODE = "LOW"; defparam DCM0.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM0.STARTUP_WAIT = "TRUE"; defparam DCM0.DFS_FREQUENCY_MODE = "LOW"; defparam DCM0.CLKFX_DIVIDE = 1; defparam DCM0.CLKFX_MULTIPLY = 2; defparam DCM0.CLK_FEEDBACK = "1X"; defparam DCM0.CLKOUT_PHASE_SHIFT = "NONE"; defparam DCM0.PHASE_SHIFT = 0;

defparam DCM1.DLL_FREQUENCY_MODE = "LOW"; defparam DCM1.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM1.STARTUP_WAIT = "TRUE"; defparam DCM1.CLKIN_DIVIDE_BY_2 = "FALSE"; defparam DCM1.DFS_FREQUENCY_MODE = "LOW"; defparam DCM1.CLKFX_DIVIDE = 2; defparam DCM1.CLKFX_MULTIPLY = 3; defparam DCM1.CLK_FEEDBACK = "1X"; defparam DCM1.CLKOUT_PHASE_SHIFT = "FIXED"; defparam DCM1.PHASE_SHIFT = 0; //synthesis translate_on endmodule // DCM_TOP