Greetings comp.arch.fpga group,
I am having some trouble implementing a ZBT or NoBL SRAM interface. I am using a Xilinx ML402 board but my trouble is generic in nature.
I am trying to divide the interface into four ports, each port having a particular time slice to read or write to the SRAM. In my case I am trying to do one write slice and three read slices, however, my issue happens with any write followed by a read.
The design is synchronous lets say at 50MHz to make the numbers easier. So a 20nS period.
Let's say at t=0nS the FPGA issues a write enable along with the write address.
I have a separate DCM clocking the SRAM and say for setup purpose I delay this clock by4 ns. So at t=4nS, the SRAM has a write command and the write address.
At t=20nS, the FPGA does a read at a specified read address. This gets clocked into the SRAM at t=24ns.
At t=40ns the FPGA issues the write data, according to the staggered data delivery architecture of the ZBT or NoBL SRAMs.
At t=44 the SRAM gets another clock. Let's say it's another write enable and address, although it doesn't matter.
After Tco(time clock to output) about 3ns, or at about t=47ns, the SRAM is outputing data for the read clock at 24ns.
There's the issue. The FPGA is outputing data from t=40ns to t=60ns and the SRAM is outputting data from 47 ns to perhaps 67ns creating a collision on the bidirectional lines.
I have thought of minimizing this affect by using a clock pin that is negatively delayed by the FPGA clock, something of the order of Tco, but it doesn't seem right that I should have to split hairs like this. Isn't the point of the ZBT architecture is so you can have write and read effortlessly meshed?
Any insight will be appreciated.
Brad Smallridge aivision dot com