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How to increase data of std_logic_vector by 1 in VHDL-2002

Hi, It is a long time headache for me to increase a data of std_logic_vector by 1.

Here are examples: LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all;

constant ONE : std_logic_vector(7 downto 0); signal Series_Number : std_logic_vector(7 downto 0); ... All followings generate errors in VHDL-2002: Series_Number

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W TX
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Reply to
andrew_b

Series_Number

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andrew_b

Reply to
W TX

Hi, I now ha another similar problem: how to change an integer to a std_logic_vector.

Here is a code snippet: signal X :integer range 0 to 15; signal Y :

Reply to
Tianxiang Weng

Hi, I now have another similar problem: how to change an integer to a std_logic_vector.in VHDL-2002.

Here is a code snippet:

signal X :integer range 0 to 15; -- X is used as an index to an array. signal Y :std_logic_vector(3 downto 0); -- Y is a device input interface so Y data type cannot change, but X may be.

Y
Reply to
Tianxiang Weng

Hi, In

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I learned the solution: Y

Reply to
Tianxiang Weng

Maybe save a copy of this:

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It has pretty good coverage on type conversions in VHDL.

Reply to
Anssi Saari

ic_vector.

Hi, Thank you. When I opened the *.pdf file and planned to save it, a surprising thing hap pened: my computer has already had a copy of it. After downloading it, I ne ver read it. Its name is "DRAFT Standard for Floating-Point Arithmetic P754

-Draft 129", I thought it is for Floating-Point Arithmetic only, and I neve r use Floating-Point Arithmetic in VHDL. After your post, I changed the pdf file name to "VHDL-Type conversion".

This time I will read it carefully.

Weng

Reply to
Tianxiang Weng

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