Hi, Based on suggestions from this group, when switching libraries from USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;
to USE ieee.std_logic_1164.all; use ieee.numeric_std.all;
this morning I really found a big new issue dealing with 'std_logic_vector' and 'unsigned'.
Here is the definition of 'unsigned' from ieee.numeric_std.vhd: type UNSIGNED is array (NATURAL range ) of STD_LOGIC;
Here is the definition of 'std_logic_vector' from ieee.stdlogic.vhd: TYPE std_logic_vector IS ARRAY ( NATURAL RANGE ) OF std_logic;
Actually one cannot see any big differences between 'unsigned' and 'std_logic_vector'.
But the following code shows big differences between the two's behaviors within a generate loop:
signal A : unsigned(1 downto 0); ...
Generate_A : for I in 0 to 3 generate ModuleX : port map ( ... A => A(I),