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How to set Xilinx compiling parameters to get PCI setup time right

Hi, I recently switched from Xilinx 6.3 to Xilinx 7.1.i4.

After the first compilation, I was surprised to find that PCI input setup time is about 1.5 ns, excellent configuration! 66MHz PCI input setup time is 3.0 ns. Usually I got 2.9xxns from 6.3 version.

But recently my compilation parameters changed and the PCI input setup time is returned back to around 3.0 ns, and most of time, it is beyond

3.0 ns that leads to an unsuccessful compilation result.

Can you give some tips on which parameter setting caused the dramatic change for the PCI input setup time?

Thank you.

Weng

Reply to
wtxwtx
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Weng,

Which part?

Aust> Hi,

Reply to
Austin Lesea

Hi Austin, CONFIG PART = XC2V1500-FG676-5.

I checked all my previous compilations.

The best one is: TIMEGRP "PCI" OFFSET = IN 3 ns BEFORE COM | 3.000ns | 1.207ns | 0 It was generated in 1/5/2006, within 2 weeks. I didn't even set those settings of compilation parameters, and just used the default values.

Now new result: TIMEGRP "PCI" OFFSET = IN 3 ns BEFORE COM | 3.000ns | 2.976ns | 1 It was generated today and you may see the dramatic differences between two compilation result. This settings of compilation parameters are set as the highest one.

but I don't know which parameter plays the important role.

Do you know it?

Weng

Reply to
wtxwtx

You're looking at poorer setup times. Have your clock-to-out times skewed as well?

The routing of the clock can give you large differences in some Xilinx devices. A clock input pin doesn't HAVE to route to the BUFG(MUX) closest to it and encounters a larger delay moving to the other side of the chip. Similarly, the DCM/DLL can use buffers and input pins not along the same side.

If clock routing is responsible for some or all of the differences, the input setup and clock-to-out times will shift the same direction; if setup time is worse, clock-to-out will be better. Sometimes the clock resources have to be LOCed to get 100% repeatability.

Reply to
John_H

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