How to set Xilinx compiling parameters to get PCI setup time right

Weng,

Which part?

Aust> Hi,

Hi Austin, CONFIG PART = XC2V1500-FG676-5.

I checked all my previous compilations.

The best one is: TIMEGRP "PCI" OFFSET = IN 3 ns BEFORE COM | 3.000ns | 1.207ns | 0 It was generated in 1/5/2006, within 2 weeks. I didn't even set those settings of compilation parameters, and just used the default values.

Now new result: TIMEGRP "PCI" OFFSET = IN 3 ns BEFORE COM | 3.000ns | 2.976ns | 1 It was generated today and you may see the dramatic differences between two compilation result. This settings of compilation parameters are set as the highest one.

but I don't know which parameter plays the important role.

Do you know it?

Weng

You're looking at poorer setup times. Have your clock-to-out times skewed as well?

The routing of the clock can give you large differences in some Xilinx devices. A clock input pin doesn't HAVE to route to the BUFG(MUX) closest to it and encounters a larger delay moving to the other side of the chip. Similarly, the DCM/DLL can use buffers and input pins not along the same side.

If clock routing is responsible for some or all of the differences, the input setup and clock-to-out times will shift the same direction; if setup time is worse, clock-to-out will be better. Sometimes the clock resources have to be LOCed to get 100% repeatability.