Re: How to use Modelsim-Altera to do the timing simulation?

Hi,all

> I use synplify or Quartus to do the synthesis. > What files should I pass to Modelsim to do the timing simulation?

The tools should spit out a .SDF file and a new Verilog or VHDL top-level file. Compile the top-level file, replacing the RTL code, and tell the simulator to apply the SDF file appropriately. For example, if your test bench is called foo_tb.v, and it instantiates your design as:

mychip uut (this, that, theother);

tell ModelSim that it should apply the .SDF to /uut and it should just work. You may also have to compile a library of Altera primatives.

I would imagine that Altera's documentation spells all of this out in gory detail :)

=a

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Andy Peters
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