Do you have a question? Post it now! No Registration Necessary
- Andy Peters
September 1, 2003, 1:59 am


The tools should spit out a .SDF file and a new Verilog or VHDL
top-level file. Compile the top-level file, replacing the RTL code,
and tell the simulator to apply the SDF file appropriately. For
example, if your test bench is called foo_tb.v, and it instantiates
your design as:
mychip uut (this, that, theother);
tell ModelSim that it should apply the .SDF to /uut and it should just
work. You may also have to compile a library of Altera primatives.
I would imagine that Altera's documentation spells all of this out in
gory detail :)
=a
Site Timeline
- » Compact FIR filters with multiplier blocks?
- — Next thread in » Field-Programmable Gate Arrays
-
- » Re: Question conserning Altera's Quartus II
- — Previous thread in » Field-Programmable Gate Arrays
-
- » Fully Comitted to LVDS as Comparitors
- — Newest thread in » Field-Programmable Gate Arrays
-
- » Kuchenka Mastercook typ 3400 programator - co w zamian
- — The site's Newest Thread. Posted in » Electronics (Polish)
-
- » transformer son analogique tv vers bluetooth puis casque
- — The site's Last Updated Thread. Posted in » Electronics (French)
-