Sure; I can't find my folder of DCM simulation notes right now, but searching the Xilinx Answer Records for "DCM" or "DCM simulation" will turn up a boatload of the DCM simulation quirks; I've listed some more of them below.
You may also want to try running a post-PAR timing simulation to see what the DCM delay looks like with the back-annotated delays.
11067 SimPrim - ModelSim Simulations: Input and Output clocks of the DCM and CLKDLL models do not appear to be de-skewed 13213 UniSim, SimPrim, Simulation - How do I simulate the DCM without connecting the CLK Feedback (CLKFB) port? (VHDL) 11344 UniSim - Variables passed to GENERICs in functional simulation are not working properly (VHDL) 18390 7.1i Timing Analyzer/TRACE - Changing the DESKEW_ADJUST parameter does not affect the DCM value (Tdcmino) 20845 6.3i UniSim, Simulation- There is a Delta-cycle difference between clk0 and clk2x in the DCM model 22064 7.1i UniSim, Simulation - There is a Delta-cycle difference between CLK0 and CLKDV in the DCM model 6362 UniSim, SimPrim, Simulation - When I simulate a DCM or CLKDLL, the LOCKED signal does not activate unless simulation is run in ps time resolution 18115 8.1i/7.1i Simulation - DCM outputs are "0" and the DCM does not lock UniSim and SimPrim VHDL models) (DCM reset requirement) 19005 Virtex-II/Virtex-II Pro, Clocking Wizard - The LOCKED signal doed noy go high for cascaded DCM when CLKDV is usedhave fun, Brian