Simulation of DCM with Xilinx 8.2 and Modelsim 6.1

Hello,

for some reason I still don't understand, when I simulate my Post Place & Route model, the DCM that was configured to introduce a delay of 2ns does not work properly. It shows a delay of 1.3 ns instead.

This is the code that I use to instantiate the DCM:

-- DCM with fixed positive phase shift (2 ns, configured with Coregen) Inst_my_dcm_a: my_dcm PORT MAP( CLKIN_IN => dsp_clk_pad_a, RST_IN => rst, CLKIN_IBUFG_OUT => open, CLK0_OUT => dsp_clk_a, LOCKED_OUT => LOCKED_a );

The input clock has a period of 10 ns (100 Mhz).

In Modelsim, this is the route and the delays from the clock input pad until some point in the circuit: