Depth of logical Circuit

Run the timing analyser. After synthesis it will use estimated timings; after place and route it will use accurate timings derived from the routing.

It will give details of the logic depth ( in LUTs rather than gates ) of the slowest n paths, according to the options you use to run it.

- Brian

Cheers Brian, I did what you suggested with the following simple boolean circuit:

library ieee; use ieee.std_logic_1164.all; entity test is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : out std_logic ); end test;

architecture struct of test is

signal t : std_logic;

begin

Cheers Brian. I wrote a very simple logical circuit consisting of two gates just to try these things out:

entity test is port ( a : in std_logic; b : in std_logic; c : in std_logic; d : out std_logic ); end test;

architecture struct of test is

signal t : std_logic;

begin

his

IMHO, the best way to do this is to add a clock to your design, register the inputs and register the outputs and then place a PERIOD constraint on the clock in your UCF file.

This will provide a more accurate number for your experimentation avoiding extra delays caused by the input and output buffers.

You will likely need to turn on the Verbose reporting feature in the timing analyzer so that paths are reported even when the timing constraint is met.

Ed McGettigan

-- Xilinx Inc.

Sorry, I assumed the context of a more complete circuit.

Follow Ed's advice : add a clock, and registers before and after the circuit itself.

Add a timing constraint to the clock.

Now. An alternative to Ed's suggestion to use verbose reporting from the timing analyzer : reduce the timing constraint period (or increase frequency) until P&R fails.

Timing analysis will now give the full and gory details of the worst n paths that failed the timing constraint, including the levels of logic you are after.

This is logical and sensible tool behaviour; if it passed timing, most people don't care about the details. But if it failed, seeing the depth of the logic depth will guide you as to what part of the design must be improved to meet timing.

(Alternatively, it may show that excessive routing delay comes from poor placement of one or more components. But that is another story)

- Brian

Hi Richard,

Xilinx has netgen tool that can help you with that.

1. running netgen on a post-synthesis netlist will create a gate-level HDL representation. For example: $ netgen -w -ofmt verilog -sim .ngc post_synthesis.v

1. running netgen on a post-MAP design file will create a gate-level HDL with placement information. For example: $ netgen -s 3 -pcf .pcf -sdf_anno true -sdf_path "netgen/map" -w -dir netgen/map -ofmt verilog -sim .ncd post_map.v

2. running netgen on a post-PAR design file will create a gate-level HDL with placement and routing information. For example: $ netgen -s 3 -pcf .pcf -sdf_anno true -sdf_path "netgen/par" -insert_pp_buffers true -w -dir netgen/par -ofmt verilog - sim .ncd post_par.v

You can also do it from ISE GUI without using command-line.

Thanks, Evgeni

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I haven't done this in a while. Is it still possible to double click an output in the ModelSim simulator and get a graphical report on all the logic leading up to that output?

Brad Smallridge AiVision