Hi, I am confused at how to set DCM generic parameters on Xilinx FPGA, I know the input clock is 84MHz, and I see my colleague set
CLKDV_DIVIDE = 1.5 CLKIN_PERIOD = 10
then it seems he can get 66MHz from output pin CLKDV.
I am confused: Does 84MHz have any use here? It seems the actual input clock frequency does not matter here, the output frequency is totally depending on how you set these parameters.
Then my question is what's the frequency of clk0? 84MHz or 100MHz?
Thanks.
Fron the Constraints guide: CLKIN_PERIOD specifies the period of the clock used to drive the CLKIN pin of the DCM. It must be specified to provide software with enough information for optimal frequency synthesis operation given an M and D value when using the CLKFX or CLKFX180 outputs. It is not needed for other DCM clock outputs. In your case, it looks like it's not used. clk0 will have the same frequency as the input clock. CLKDV will be 2/3 of this frequency (56 MHz in your case).
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