I am using v2pro 100 device with core clk speed of 200 mhz and am running rocket io, aurora and supporting logic at 156.25Mhz. I am noticing unusually high skews on these clocks. here is an excerpt from par report.
+-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+ | core_clk | BUFGMUX6S|Yes | 6096 | 1.175 |
2.654 |
+-------------------------+----------+------+------+------------+-------------+ | ssp_tx_gclk1 | BUFGMUX2S|Yes | 169 | 0.267 |
2.508 |
+-------------------------+----------+------+------+------------+-------------+ | ssp_tx_gclk2 | BUFGMUX0S|Yes | 169 | 0.158 |
2.631 |
+-------------------------+----------+------+------+------------+-------------+ | core_clk_dv2 | BUFGMUX1P|Yes | 1358 | 1.120 |
2.604 |
+-------------------------+----------+------+------+------------+-------------+ | nfclk | BUFGMUX7P|Yes | 2012 | 1.411 |
3.196 |
+-------------------------+----------+------+------+------------+-------------+ Although this skew might be for two flops which are at farthest in the chip and probably not in the path it still does seem mighty large. Is there anything we can do to reduce this skew. We are using DCM and these clock as well.
samir