Initializing data in EAB ram

Jun 22, 2004 1 Replies
R

I am using an EAB as a RAM for program storage for an MCU in an Altera ACEX FPGA. But I can't seem to find info on how to initialize the RAM. I will at least need a boot strap program to read an external Flash into the RAM. I found information about creating MIF files and RIF files. But they don't say much about how they get used. Can anyone give me the details? I assume this initialization data goes into the bit stream using the tools, no? Is there a way to initialize the RAM in a VHDL simulation other than to use the variable initialization of VHDL? That seems very messy.



If the EABs can not be initialized, I guess I will have to provide an external means of loading the RAM after the chip has been configured.


Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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R

My recommendation is to use the MegaWizard plugin manager and examine the generated VHDL to see how they do it, then you have the option to roll your own. Basically you pass the MIF file as a Generic to the instantiated component. It works smoothly. That is, for Stratix... The options for ACEX may be different.

COMPONENT altsyncram GENERIC ( INIT_FILE : STRING := "YourFile.mif"; INIT_FILE_LAYOUT : STRING := "PORT_A"; );

Yes. See the Quartus Help on Opening Embedded RAM, and Update Simulator with Current Memory. You have to insert a simulation breakpoint and do it then... (Though at this very moment I'm trying to do this with a MegaRAM, and struggling.)

Hope this helps,

-rajeev-

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