VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)

I'm new to VHDL and I want to learn as with examples. I want to build a 16,24 or 32 bit counter for quadrature encoder signals (ie A,B signals). Can someone help me how to create following functionality in VHDL ?

Inputs are (1,2) A, B = A,B quadrature signals (from encoder) ( 3) IDX = Index (from encoder) ( 4) RST = Reset (Low->Reset counter) ( 5) S/P = Serial/Parallel output select (High->Serial output, Low->Parallel output) (6,7) A1,A0 = Output byte selector A1,A0 ([A1,A0] --> [0,0] ->Counter byte0 output, [0,1]->Counter byte1, [1,0]->Counter byte 2, [1,1]->Counter byte3) ( 8) OE = Output Enable (Low->Enabled, High ->High state output) ( 9) SCLK = Serial out clock (If S/P is high (ie serial out selected) then Low to High transition output one bit of the counter value starting from LSB to MSB)

Outputs are (1,2,3,4,5,6,7,8) D0..D7 = Counter value output (A1,A0 selects which byte will be output) (1) = Serial output (if serial output selected on S/P )

Reply to
<Patrick Harold>
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Taking a VHDL class are we?

Reply to
jamie

(ie

You may also need an input to "freeze" the count before you read it. In other words a register to save all bytes of the present count, while allowing the counter to continue. However, I did one design that automatically latched all bytes when reading the Least Significant byte leaving you free to read the other bytes at will.

Sorry I can't help with the VHDL, I've done the same design many times using Schematic and/or vendor specific generated macros.

--
Greg
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Reply to
Gregory C. Read

Take a google for Opencores. They've got an example there. Examine it closely, or you'll learn nothing from it.

Paul Burke

Reply to
Paul Burke

One thing you might consider is to use a smaller counter that is automatically cleared when read. The count thats read (delta) can then be added to a software maintained count of any size. This is often faster on systems with slow I/O but fast CPUs (micros with SPI or PCs for example)

I have an example of a dual 12 bit quadrature counter that will fit in a XC95C72Xl CPLD (~2.00) that uses this delta counter design. Too big to post here but I can email it if you are interested.

Peter Wallace

Reply to
Peter Wallace

I imagine if you'd ask a more specific question regarding some attempt you've made in VHDL, you might get some better help. Or do you have no idea at all where to start?

Jon

Reply to
Jonathan Kirwan

(ie

What difference does it make if he is taking a VHDL class and needs help. He seems honest, and forthcoming. "I'm new to VHDL...." etc. Bro, if I knew VHDL I would personally help you, but last time i saw VHDL was in college about 11 years ago.

Yall should help the guy, ESPECIALLY if he is a student.

Reply to
George

Try the newsgroup

comp.lang.vhdl

Reply to
ALuPin

Dear George,

I would like to thank you for your understanding. Unfortunatelly I'm not student. (I'm too old to be a student.. When I was student, I was working with tubes (not even with transistors) ). It is not so easy in my age to keep track with the all this new technologies. I'm trying my best to follow the technology. I recently started to study the VHDL. I'm almost on the "page one" of the VHDL study and want to learn by implementing simple little projects. Thank you once again for your understanding. Regards.

Reply to
<Patrick Harold>

Thank you. I'm afraid, I did not realized that there exists "comp.lang.vhdl" group.

Reply to
<Patrick Harold>

Sorry Patrick, I'm use to students trying to do there homework online...

Search amazon (and also google) for VHDL resourses. I'd suggest you make small devices and work up (make an invertor, make a flip-flop). Doing it that way you will get use to the language and then you can focus on what you really want to build.

Regards,

Jamie

Reply to
jamie

Reply to
<Patrick Harold>

I first learned on tube designs, as well. Transistors were the 'new fangled' thing for me, later on. My first impressions, back when I was first reading about transistors, were that tubes were quite superior, as transistors required quite a bit more feedback to remain faithful to their inputs over a range. Oh, well. Long time ago.

I don't have a lot of books on VHDL, but one that really helped me when I knew nothing at all was a book by a British guy who moved to Alabama some years back called, "HDL Chip Design." It provides a nice introduction that assumes very little by way of understanding and gives you a little history. Elsewhere in the book you will see both VHDL and Verilog examples of the same designs and he covers a great many of the basics. ASICs and FPGAs are discussed, with their attendant differences in emphasis when designing, but not so much that you get overwhelmed. Examples are given to show you how changes in an approach can yield improvements. He discusses RTL and gate level optimizations in a way that a newbie can easily fathom, I believe. In short, regardless of possible errors in the book today, it made a very easy path for me to get my first VHDL designs up and running on a real FPGA board. I went from not even knowing a single keyword of VHDL to my first properly functioning 4-bit adder and 7-segment digit display driver circuit in less than a week. And the code wasn't borrowed or stolen, I'd written it from scratch by myself.

Which books might speak better to you, I don't know. But that one got me started and gave me enough of the basics that I could then start reading the VHDL others have written with some understanding and also begin to understand other FPGA issues the book didn't cover, like floorplanning. (obviously, I don't care about ASICs as I'm unlikely to be designing any unless I come into some cash I don't otherwise need.)

Jon

Reply to
Jonathan Kirwan

Tubes are not all that different from transistors, especially MOSFETs. They are considerably bulkier, require much higher voltages, need heaters, and dissipate much more power. However they are all 'gain blocks'.

However you should learn to post correctly. Your answer belongs AFTER (or intermixed with) the material to which you reply, AFTER snipping out portions irrelevant to your answer. This is known as bottom-posting, and is always acceptable. What you are doing is called top-posting, which makes articles virtually unreadable and allows them to grow indefinitely, like a cancer.

--
"I'm a war president.  I make decisions here in the Oval Office
 in foreign policy matters with war on my mind." -         Bush.
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Reply to
CBFalconer

First of all split up your design into modules with a more specialized task. I would suggest :

- A module for doing the conversion of the input signals A,B,IDX into up and down counting pulses for the next stage.

- a up-down counter 32/16

- the output stage for parallel output

- a parallel/serial converter and its output stage

This may be sufficient for learning purposes. In practice, if you really want a working design you have to spend some thoughts about the following :

- what happens when you are reading out during a counting pulse from the encoder

- what happens if the encoder signals are noisy and changing to fast or counting continuosly up and down

- metastability

Last of all I would add a clock signal and make it a synchronous design.

Best regards

--
Klaus Falser
Durst Phototechnik AG
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Reply to
Klaus Falser

So did you download the Opencores example?:

Paul Burke

Reply to
Paul Burke

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