Estimate area from SPICE netlist

Could some SPICE guru please help ? Suppose I have a SPICE netlist, consisting of semiconductor MOSFETs, semiconductor resistors etc., So the area occupied by these devices can be estimated easily. Now how do I estimate the area for the interconects ? Any hints, suggestions would be of immense value.

Reply to
Daku
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You need the design rules for the process.

From those you can deduce an area equation for each device type from L and W.

In PSpice, netlisting is done via a "template". This template can calculate anything appearing between curly brackets {..}

In PSpice you can have multiple netlisting templates. I typically have four:

(1) "Template, for PSpice simulation

(2) "HSpice", if I need to hand-off to a user of slow-expensive tools ;-)

(3) "LVS", for my layout guy... only has L and W, no parasitics such as AD, AS, PD...

(4) "ChipArea", which implements the area equations.

The snag... PSpice can read the equations and do its thing internally, but never shows the "finished" calculated values in the netlist or output file.

So-o-o-o. I have this son, Aaron, who can write software quite nicely (he's chief network engineer for the largest call-center company in the world :-)

Aaron has written several text processors for me that can do such things as take binned models into PSpice.

Recently he wrote one that computes everything from the "ChipArea" template and displays a final active area value for the chip core.

At the moment we're not planning to sell (or share) these text processors. Maybe some day. ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Ever tried it with LTSpice, or think Aaron's software routine can work with it?

Why not? There'd be Tanner Tools and then there'd be Thompson Tools :-)

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Reply to
Joerg

What, be helpful? For free?

John

Reply to
John Larkin

Doesn't have to be free :-)

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Reply to
Joerg

I don't know. I've used LTspice simulation only with LTspice schematics, so I'm not familiar with the "template" options (if any, a quick look, I find nada).

Yet I would expect Mike to have covered that in some way.

The area calculation doesn't require anything other than the capability to netlist using an area-specific template.

Aaron's program reads in the netlist and does the calculations without needing the parent simulator/netlister.

We've contemplated that, but neither of us has much time. Creating a commercial product is far more difficult than making a non-GUI, simply run it, and look at the revised netlist kind of product.

Plus you need to copy-protect and license it ;-) Otherwise no money.

Next up is a piece-wise-linear curve fitter.

Based on a suggestion by Tim Wescott...

Message-ID:

I've reduced that suggestion to an algorithm that Aaron can implement. ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
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       The Ground Zero Mosque IS Appropriate When Renamed...
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Reply to
Jim Thompson

Unfortunately the market is small. Enumerating all the analog chip designers in the world doesn't even require removing your shoes :-) ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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       The Ground Zero Mosque IS Appropriate When Renamed...
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Reply to
Jim Thompson

With analog circuit board level designers it's even worse :-(

But: Such a tool doesn't have to be sold for $19.99. If it saves hours of grunt work per chip design a few hundred bucks are easily ok. Times

50 or so would buy a lot of your $100 lunches. Well, maybe only half as many as you think because now you'd have to invite Aaron and his wife to those.
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Reply to
Joerg

True enough. I'll talk to Aaron. ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
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       The Ground Zero Mosque IS Appropriate When Renamed...
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Reply to
Jim Thompson

Might also try to properly copyright it and then talk with Mentor or Cadence about a license :-)

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Reply to
Joerg

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

While I'm sure he could readily do so, I'm not so sure he would have necessarily bothered since he presumably never intended to interface the schematics with any simulator other than his own. But I don't really know...

Is it a flat or hierarchical netlist? If it's flat this sure seems like a very straightforward kind of program to write, like no more than a hundred or so lines of code... (assuming you're using a high-enough level language that things like string parsing routines are already built-in...)

Doesn't the GUI only need to be a button for, e.g., "Select netlist file...," a button for "Analyze!," and a text box indicating the total area? Or is it rather fancier than that?

It's probably not worth your time to copy-protect it -- for this kind of software, it I can't imagine that more than, say, 1% of the people who *would* pirate it could *ever* be made to pay for it assuming you could design in 100% effective copy protection somehow.

What was the title of the message? That link isn't working for me...

Check out these guys:

formatting link
-- the guy who runs the place, Bob Wood, has just one or two guys writing all that software. The prices strike me as too high for hobbyists, but definitely cheap enough for those who are being paid for their time. He forces you to re-activate the software every time you install it on a new computer, which is a significant negative, but not so much that my CPOE hasn't purchased some of those programs.

---Joel

Reply to
Joel Koltner

The area calculation depends only on the ability to netlist with a "ChipArea" template.

Right now it's flat... makes it easier to account for multiple instances, though I see no reason it couldn't be made to handle hierarchical netlists.

Nope, that's all.

"Data Reduction... Further Questions"

...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
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       The Ground Zero Mosque IS Appropriate When Renamed...
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Reply to
Jim Thompson

Hi Jim,

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

If the hierarchy still stores every instance of a sub-circuit, yes... but if the hierarchy allows you to have, e.g., a particular sub-circuit somewhere and then it's referenced multiple times by another circuit elsewhere, then your program has to start remembering all results from each sub-circuit too. Not too hard, certainly, but definitely no longer "fall off a log"-easy as the flat case is.

Which language is the current tool written in?

I seem to recall you posted that dB/voltage/dBm/etc. conversion tool he wrote which was done in Visual BASIC.

Thanks!

---Joel

Reply to
Joel Koltner

Whatever the latest "C" is.

...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

       The Ground Zero Mosque IS Appropriate When Renamed...
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Reply to
Jim Thompson

Reply to
Daku

-)

=A0 =A0 ...Jim Thompson

=A0 =A0| =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

=A0|

=A0 =A0 =A0 |

So you are saying there are ten or less analog IC designers in the world? Or do you have a few hundred fingers on each hand?

Reply to
miso

No, he's saying that there are less than ten analog IC designers like him.

I think that is fortunate.

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Thanks,
Fred.
Reply to
Fred Bartoli

:-)

=A0 =A0 =A0 ...Jim Thompson

=A0 =A0 =A0| =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

=A0 =A0|

=A0 =A0 =A0 =A0 |

=A0|

|
.

If you tossed in RF chips (hey, they are analog), there are probably a few thousand analog IC desgners. (Most of these RF chips are just transistors and biasing, not systems on a chip.) RAM design is analog.

Basically it was a silly statement. Even the old Intel analog group had more than 10 designers. In traditional mixed mode design, there are probably a thousand designers world wide.

Getting back to the original questions, such programs exist to estimate die size from netlist, but I don't know of any commercial products. A low tech method is the paper doll chip plan. Cut out plots of old op amps, add large components and bonding pads, then plop them on paper. Some chips are strictly sized by the periphery, i.e. they have multiple circuits driving pads. For those, you layout the pad driver and determine the size of the hole in the middle, which hopefully can contain the rest of the circuitry.

Reply to
miso

[snip]

I'm mostly now on 3-metal-layer processes, so I only estimate plus-10% for interconnect.

In the past, on bipolar single-layer-metal, I'd often double or triple active area, depending on the "busy-ness" of the circuit. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

       The Ground Zero Mosque IS Appropriate When Renamed...
            The Obama Monument to American Impotence
Reply to
Jim Thompson

Isn't that common these days? The design I am involved in sort of defaulted to three metal layers. Meaning we can have a ground plane on the chip. Yeehaw! I almost jumped out of my chair.

[...]
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Regards, Joerg

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Reply to
Joerg

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