LTSpice Slowdown

The usual reason that simulations slow down is that you've included a very fast component, and the simulation would go unstable if it tried to run with the time-step that used to work.

My Ph.D. thesis includes a reference to H.H. Rosenbrock and C. Storey's "Computational Techniques for Chemical Engineers" Vol 7 of of Pergamon Press's international sereis of monographs in chemical engineering, which spelled out the problem in some detail.

In LT Spice you often see the problem when you try and stick a real comparator into a circuit you are simulating. Fake comparators - aka logic elements - tend to be more forgiving.

--
Bill Sloman, Sydney

Not necessarily; I've seen many a simulation where it just crawls, even while the d(something)/dt at all points is well behaved. And the TRTOL is such that it should've recovered by then.

The upside to SPICE is that, for all the shit we engineers fling at it, it does amazingly well. Computational simulation is *hard*. I would hate to even try to write one from the ground up, and I'm grateful that others have already tried, and for the most part, succeeded.

The downside is, as powerful as SPICE is, it breaks like a pane of glass on so many things, and, the failure modes are exceedingly complex and nonlinear. So, sometimes... either it works, or it doesn't.

A very typical case is a circuit which runs with a resistor of X, but slows down or fails at X + delta, whatever increment that may be. Highly nonlinear systems share the characteristic of sensitivity to initial conditions, system parameters, etc.

That said, even given the fact of "highly nonlinear", there are still many "common" gotchas with SPICE, which the OP may be more or less guilty of. Knowing the simulation and being able to repeat the problem would be helpful.

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com

"The usual reason" allows lots of other explanation of why simulation just crawls.

And the problem isn't that the d(something)/dt is high at some point, but r ather that some point in the circuit would allow it to become big, if the s tep-size was large enough. Including a very short-time-constant component i n an otherwise innocuous circuit can do just that - the computed dV/dts nev er get large, but they get calculated very frequently.

-- Bill Sloman, Sydney

It is the same simulation of the LTC3109 that I've been posting about. The initial schematic I was given by LT simulates nicely. But it isn't exactly the circuit I will be building. Plus I seem to have broken the shutdown circuit with the same change.

I am guessing the main change is the fact that the source, inductor, switch loop is no longer referenced to ground other than through a 100 Meg resistor I added to make the simulation work. Also, with the original arrangement, each of the two inputs had a separate voltage source feeding it, now they are connected to the same source with opposite polarity. This is the issue I wanted to correct. The real circuit uses two inputs for getting power depending on the polarity of the source. TEGs can run positive or negative depending on if they are hot or cold compared to their reference.

I replaced the PMOS FETs with an analog switch. I pretty well understand how they work. After all, they are much more digital in nature, lol. The simulation is running but veeeery slooooowly, about 6 us/s... :( I'm only trying to get 20 ms from it as this point.

But there is a new wrinkle. The B section started up with the input voltage positive. The A section is the one that should be working for positive inputs. But maybe that has to do with the switch affecting the circuit with no Vdd. After all, the output of the voltage converter has to power the switch. We'll see if it switches over once some voltage shows up on the outputs.

--

Rick

Here is an example that to my eye has no rhyme or reason. I wanted to simulate the switch model I just downloaded to make sure I have the symbol right. I had nothing on the output of the switched pin and the simulation crawled... or did it crash, I don't recall. So I added resistors. Then it ran just fine. I decided to measure the switch resistance and changed the load resistor to something small like 0.1 ohm since the switch is in the ballpark of 200 mohms. That crawled on the control pin change, 10 ps/s!

I changed the resistor to 0.15 ohms and it ran instantly. Just to confirm my estimate for the switch resistance I changed it to 275 mohm. That is back to crawling at 10 ps/s... go figure.

--

Rick

You've most likely created a circuit with an instability, causing the simulator to "hunt".

Post your .ASC file. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Try the Gear integrator. It's better for systems with widely different time constants (aka 'stiff' systems).

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

Ground reference is one of those "newbie mistakes" -- you're approaching a singular matrix error, which means, it can't solve the matrix uniquely. Literally, it's sitting on top of ice and can't find where it needs to be referenced to.

SPICE requires a ground reference.

If the resistance is large but finite, sometimes it will soldier on anyway, but at a crawl, because the matrix is near-singular. It's using small timesteps to attempt to avoid rounding errors that would make it singular.

Same goes any time you have transformers (the isolated sides need to be referenced to ground somehow), or inductors in parallel (the current flowing between them is undefined -- add at least one series resistor to the loop to allow that current to decay so it can find a DC initial value of zero for that loop).

The 100M to ground isn't necessary if you have RSHUNT=1e8 set, but it crawls all the same. Sometimes, it is illuminating to remove such resistors or set RSHUNT very much higher, so that the simulator actually tells you you've screwed up, rather than chugging on slowly.

If by switch you mean an ideal switch (simulation) component, that can make things worse because switches are notoriously hard to simulate. They're fast when they work, but they're trouble when they don't. MOSFETs have the advantage that they are generally well conditioned, so although they may cost more CPU cycles, they tend not to fail outright.

On the other hand, I've seen IGBT models fail regularly. They're usually built out of standard components, but they often encounter problems during cutoff (after switching, where d(stuff)/dt is small, but as Ic is decaying to zero).

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com

Ahmmmm.... Over millions and millions of simulations, I have never found gear and trap to have any speed or ability to converge differences. However, gear will eliminate the low level triangle numerical noise at the expense of causing some oscillators to not oscillate.

Kevin Aylward

- SuperSpice

That's where I started. When I changed the circuit to remove the ground the simulation wouldn't run. I added the 100Meg resistor and it ran but slowly. Changing the value of the resistor seems to make no improvement to run time.

I am using the model for the ADG884. When I remove the switch entirely the simulation does not speed up.

It does other things that are odd. I don't really know how to shutdown this chip, LTC3109. The circuit LTC suggested is the end to end PMOS FETs. But they don't work with the single TEG. Since I don't get how they are supposed to be working and no one here was willing to help me understand, I replaced them with the analog switch.

I'm not sure yet that this works any better. The simulation seems to be very sensitive to all sorts of things so that the switching circuit won't start up depending. It usually starts up on one side, but won't restart when the input polarity reverses. Then that side starts up when some other part of the circuit activates such as the OUT2 enable or the analog switch activates and then releases. The good news is that when the switcher is not running the simulation runs a lot faster. lol

I heard back from John Weber with LTC and he recommended I bump the RAM parameter in the controls. That helps with the speed some. But I still need to figure this out. I don't know why they sent me a circuit design with two input power sources... unless that is how they got the simulation to run quickly. Too bad that isn't the circuit I want to build.

--

Rick

I use gear exclusively. Trap stability is terrible, so you get numerical ringing on switching edges constantly, for example. At least in most; I haven't played nearly enough in LTSpice to know if the "modified" version addresses that.

Many circuits I've seen will run for 10s or 100s of microseconds, then halt and catch fire. Even on gear 2. Bumping that to 4th order seems to slow down the simulation only moderately, while smoothing out the simulation rate and avoiding those... singularities, or whatever you might call them, from popping up. Of course, sometimes that doesn't help, either.

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com

On 11/25/2014 10:02 AM, Jim Thompson wrote:

I think this is the third post of this design. There are two files, a model for the switch and the LTC3109 circuit file.

****************************** Model for the analog switch There may be wrapped lines, this can be downloaded from ADI adg884.cir

• ADG884 MACROMODEL

• Description: Converter

• Generic Desc: DUAL 2:1 MUX. IC.

• Developed by: Y.WONG

• Revision History: 08/10/2012 - Updated to new header style

• 1.0 (09/2008)

• Copyright 2012 by Analog Devices, Inc.

*

• Refer to
  formatting link
  for License Statement. Use of this model

• indicates your acceptance of the terms and provisions in the License Statement.

*

• BEGIN Notes:

*

• Not Modeled:

*

• Parameters modeled include:

*

• END Notes

*

• Connections

• 1 = VDD

• 2 = S1A

• 3 = D1

• 4 = IN1

• 5 = S1B

• 6 = GND

• 7 = S2B

• 8 = IN2

• 9 = D2

• 10 = S2A

***************** .SUBCKT ADG884 1 2 3 4 5 6 7 8 9 10

X1 2 3 4 1 6 HIGHONSWITCH X2 5 3 4 1 6 LOWONSWITCH X3 10 9 8 1 6 HIGHONSWITCH X4 7 9 8 1 6 LOWONSWITCH DIN1A 4 1 DX DIN1B 6 4 DX DIN2A 8 1 DX DIN2B 6 8 DX CIN1 4 6 2p CIN2 8 6 2p CC1A1B 2 5 0.063p CC2A2B 10 7 0.063p CC1A2A 2 10 0.063p RC1A2A 2 10 4.458E7 CC1B2B 5 7 0.063p RC1B2B 5 7 4.458E7

.MODEL DX D(IS=1E-12 N=0.5 RS=0.1) .ENDS

****************

• Logic High On Switch

*

• Connections

• 101 = S

• 102 = D

• 103 = VIN

• 104 = VDD

• 105 = GND

*****************

.SUBCKT HIGHONSWITCH 101 102 103 104 105 x1 103 104 105 108 BUFF X2 108 109 104 105 VSENSE X3 109 105 110 ENABLEDELAY X4 101 102 110 104 105 SWITCH

*MODELS USED .ENDS

****************

• Logic Low On Switch

*

• Connections

• 101 = S

• 102 = D

• 103 = VIN

• 104 = VDD

• 105 = GND

*****************

.SUBCKT LOWONSWITCH 101 102 103 104 105 x1 103 104 105 108 NOTGATE X2 108 109 104 105 VSENSE X3 109 105 110 ENABLEDELAY X4 101 102 110 104 105 SWITCH

*MODELS USED .ENDS

*****************

• BUFF LOGIC

*

• Connections

• 201 = INPUT

• 202 = VDD

• 203 = GND

• 204 = OUTPUT

***************** .SUBCKT BUFF 201 202 203 204 SBUFF 205 203 201 203 SMOD2 RBUFF 205 202 5G EBUFFER 204 203 205 203 1

*MODELS USED .MODEL SMOD2 VSWITCH(RON=1E-3 ROFF=1E11 VON=0.8 VOFF=2.0) .ENDS

*****************

• NOT LOGIC

*

• Connections

• 201 = INPUT

• 202 = VDD

• 203 = GND

• 204 = OUTPUT

***************** .SUBCKT NOTGATE 201 202 203 204 SNOT 205 203 201 203 SMOD2 RNOT 205 202 5G EBUFFER 204 203 205 203 1

*MODELS USED .MODEL SMOD2 VSWITCH(RON=1E-3 ROFF=1E11 VON=2.0 VOFF=0.8) .ENDS

****************

• Switch

*

• Connections

• 201 = S

• 202 = D

• 203 = VIN

• 204 = VDD

• 205 = GND

*****************

.SUBCKT SWITCH 201 202 203 204 205

*ANALOG SWITCH S1 201 208 203 205 SMOD1 S2 204 207 203 205 SMOD2 S3 204 207 201 205 SMOD3 S4 204 207 202 205 SMOD3 RD 207 205 5G S5 208 202 207 205 SMOD4

DS1 201 204 DX DS2 205 201 DX DD1 202 204 DX DD2 205 202 DX

*ON OFF ISOLATION* CSD 201 202 63.789p

*BANDWIDTH CSB 201 204 21p CDB 202 204 21p

*CHARGE INJECTION CGS 201 203 85p CGD 202 203 85p

*MODELS USED .MODEL SMOD1 VSWITCH(RON=0.28 ROFF=4.441E4 VON=2.0 VOFF=0.8) .MODEL SMOD2 VSWITCH(RON=1E-3 ROFF=1E11 VON=2.0 VOFF=0.8) .MODEL SMOD3 VSWITCH(RON=1E-3 ROFF=1E11 VON=0.5 VOFF=0.6) .MODEL SMOD4 VSWITCH(RON=1E-3 ROFF=4E10 VON=2.0 VOFF=0.8) .MODEL DX D(IS=1E-12 N=0.5 RS=0.1) .ENDS

*****************

• ENABLE DELAY

*

• Connections

• 301 = INPUT

• 302 = COM

• 303 = OUTPUT

***************** .SUBCKT ENABLEDELAY 301 302 303

EENBUFFER 304 302 301 302 1 RFEN 304 306 50k CFEN 306 302 2.0p DBREAKEN 306 305 DZ RBEN 305 304 9k EENBUFFEROUT 303 302 306 302 1

*MODELS USED .MODEL DZ D(IS=1E-14 N=0.04) .ENDS

*****************

• OPERATING VOLTAGE

*

• Connections

• 601 = INPUT

• 602 = OUTPUT

• 603 = VDD

• 604 = GND

***************** .SUBCKT VSENSE 601 602 603 604 SD1 601 606 603 604 SMOD3 SD2 606 607 603 604 SMOD4 RD0 607 604 5G EBUFFER 602 604 607 604 1

*MODELS USED .MODEL SMOD3 VSWITCH(RON=1E-3 ROFF=1E11 VON=2.7 VOFF=2.6) .MODEL SMOD4 VSWITCH(RON=1E-3 ROFF=1E11 VON=5.5 VOFF=5.6) .ENDS

****************************** The next to last line might wrap, the double dashes should be on the same line with the other double dash which I assume is a comment. 3109_Switch_single_TEG.asc

Version 4 SHEET 1 3380 1564 WIRE 640 96 544 96 WIRE 736 96 640 96 WIRE 1120 96 736 96 WIRE 1280 96 1168 96 WIRE 1408 96 1280 96 WIRE 1440 96 1408 96 WIRE 1568 96 1504 96 WIRE 1616 96 1568 96 WIRE 1936 96 1872 96 WIRE 2320 96 1936 96 WIRE 1120 128 1120 96 WIRE 1168 128 1168 96 WIRE 2320 128 2320 96 WIRE 1408 192 1408 96 WIRE 1440 192 1408 192 WIRE 1536 192 1504 192 WIRE 1584 192 1536 192 WIRE 1616 192 1584 192 WIRE 1936 192 1872 192 WIRE 2208 192 1936 192 WIRE 640 240 640 96 WIRE 1168 240 1168 208 WIRE 2320 240 2320 208 WIRE 1120 288 1120 208 WIRE 1584 288 1120 288 WIRE 1616 288 1584 288 WIRE 1936 288 1872 288 WIRE 2208 288 1936 288 WIRE 2208 304 2208 288 WIRE 1536 336 1536 192 WIRE 1536 336 1360 336 WIRE 640 384 640 320 WIRE 1616 384 640 384 WIRE 1936 384 1872 384 WIRE 2128 384 1936 384 WIRE 2208 384 2208 368 WIRE 2128 400 2128 384 WIRE 640 480 640 384 WIRE 736 480 640 480 WIRE 1120 480 736 480 WIRE 1280 480 1168 480 WIRE 1408 480 1280 480 WIRE 1440 480 1408 480 WIRE 1568 480 1504 480 WIRE 1616 480 1568 480 WIRE 1936 480 1872 480 WIRE 1968 480 1936 480 WIRE 2048 480 2032 480 WIRE 2128 480 2128 464 WIRE 640 512 640 480 WIRE 1120 512 1120 480 WIRE 1168 512 1168 480 WIRE 1408 576 1408 480 WIRE 1440 576 1408 576 WIRE 1536 576 1504 576 WIRE 1584 576 1536 576 WIRE 1616 576 1584 576 WIRE 1936 576 1872 576 WIRE 1968 576 1936 576 WIRE 2048 576 2032 576 WIRE 640 608 640 592 WIRE 1168 624 1168 592 WIRE 1120 672 1120 592 WIRE 1584 672 1120 672 WIRE 1616 672 1584 672 WIRE 1888 672 1872 672 WIRE 1936 672 1888 672 WIRE 2000 672 1936 672 WIRE 2000 688 2000 672 WIRE 544 768 544 96 WIRE 1616 768 544 768 WIRE 1888 768 1888 672 WIRE 1888 768 1872 768 WIRE 2000 768 2000 752 WIRE 704 848 592 848 WIRE 832 848 704 848 WIRE 976 848 912 848 WIRE 1056 848 976 848 WIRE 1168 848 1056 848 WIRE 1616 864 1584 864 WIRE 1904 864 1872 864 WIRE 1584 880 1584 864 WIRE 1904 880 1904 864 WIRE 1360 896 1360 336 WIRE 1360 896 1248 896 WIRE 592 912 592 848 WIRE 1168 912 1104 912 WIRE 1056 944 1056 848 WIRE 1168 944 1056 944 WIRE 1536 992 1536 576 WIRE 1536 992 1248 992 WIRE 1104 1008 1104 912 WIRE 1168 1008 1104 1008 WIRE 592 1056 592 992 WIRE 1104 1056 1104 1008 WIRE 1184 1056 1184 1040 WIRE 1232 1056 1232 1040 WIRE 1280 1056 1232 1056 FLAG 1168 240 0 FLAG 1584 880 0 FLAG 1168 624 0 FLAG 1904 880 0 FLAG 2000 768 0 FLAG 2048 480 0 FLAG 2048 576 0 FLAG 2128 480 0 FLAG 736 96 IN+ FLAG 736 480 IN- FLAG 1936 384 OUT FLAG 1104 1056 0 FLAG 1184 1056 0 FLAG 592 1056 0 FLAG 1568 96 C1A FLAG 1584 192 C2A FLAG 1584 288 SWA FLAG 1568 480 C1B FLAG 1584 576 C2B FLAG 1584 672 SWB FLAG 1936 672 VAUX FLAG 976 848 SW FLAG 1280 96 TA FLAG 1280 480 TB FLAG 1936 576 STORE FLAG 1936 480 LDO FLAG 2208 384 0 FLAG 1936 288 OUT2 FLAG 704 848 V3+ FLAG 640 608 0 FLAG 1936 192 Pgood FLAG 1936 96 OUT2_EN FLAG 1280 1056 VAUX FLAG 2320 240 0 SYMBOL PowerProducts\\LTC3109 1744 480 R0 SYMATTR InstName U1 SYMBOL cap 1504 80 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL cap 1504 176 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 470p SYMBOL ind2 1104 112 R0 WINDOW 0 0 43 Right 2 WINDOW 3 1 76 Right 2 SYMATTR InstName L1

SYMATTR Type ind SYMATTR SpiceLine Rser=85m SYMBOL ind2 1184 112 M0 WINDOW 0 0 41 Right 2 WINDOW 3 0 75 Right 2 SYMATTR InstName L2 SYMATTR Value 75m SYMATTR Type ind SYMATTR SpiceLine Rser=305 SYMBOL cap 1504 464 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 1n SYMBOL cap 1504 560 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 470p SYMBOL ind2 1104 496 R0 WINDOW 0 1 41 Right 2 WINDOW 3 1 75 Right 2 SYMATTR InstName L3

SYMATTR Type ind SYMATTR SpiceLine Rser=85m SYMBOL ind2 1184 496 M0 WINDOW 0 -2 41 Right 2 WINDOW 3 1 75 Right 2 SYMATTR InstName L4 SYMATTR Value 75m SYMATTR Type ind SYMATTR SpiceLine Rser=305 SYMBOL voltage 640 224 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PWL(0s 0V 2.5ms -20mV 2.53ms -20mV 10ms -60mV 20ms 60mV) SYMBOL cap 1984 688 R0 SYMATTR InstName C5

SYMBOL cap 1968 496 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C6

SYMBOL cap 1968 592 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C7

SYMBOL cap 2112 400 R0 SYMATTR InstName C8

SYMBOL res 928 832 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 10K SYMBOL voltage 592 896 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 34 65 Left 2 SYMATTR Value PULSE(0 2 55ms 10ns 10ns 2ms 10ms) SYMATTR InstName V3 SYMBOL cap 2192 304 R0 SYMATTR InstName C9

SYMBOL res 624 496 R0 SYMATTR InstName R2 SYMATTR Value 10Meg SYMBOL ADG884 1200 992 R0 SYMATTR InstName U2 SYMBOL voltage 2320 112 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 34 65 Left 2 SYMATTR Value PULSE(0 2 21ms 10ns 10ns 3ms 40ms) SYMATTR InstName V2 TEXT 1144 96 Bottom 2 !K1 L1 L2 .98 TEXT 1144 480 Bottom 2 !K2 L3 L4 .98 TEXT 1688 952 Left 2 !.tran 0.070 TEXT 1352 -160 Left 2 !*SRC=DMP2240UDM;DI_DMP2240UDM;MOSFETs Enh;20.0V

2.00A 0.150ohms Diodes Inc MOSFET\n.MODEL DI_DMP2240UDM PMOS( LEVEL=1 VTO=1.00 KP=11.9u GAMMA=1.24\n+ PHI=.75 LAMBDA=514u RD=21.0m RS=21.0m\n+ IS=1.00p PB=0.800 MJ=0.460 CBD=81.1p \n+ CBS=97.4p CGSO=720n CGDO=600n CGBO=1.88u )\n* -- Assumes default L=100U W=100U -- TEXT 1272 944 Left 2 !.inc adg884.cir

--

Rick

Well, I disagree. Again, its the millions of sims bit. Its my 37 1/2 hour a week day job. If it were that bad, it would never have been implemented in spice at all.

I always default to Trap, and only change to gear on the few occasions that the triangles start appearing.

Sure, that does happen., but not that often, relatively, in my experience. Well, if there are no inductors...

Most problems are due to poor models. It is somewhat stunning just how bad some manufactures models are. To be quite blunt, some model writers are clearly completely clueless as to how spice works, so that they can actually write a decent model.

Kevin Aylward

- SuperSpice

'Tis why I love TANH so much... soft limits keep Spice happy ;-) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Ah, well... excuuuuse me if my simulations represent reality... :^)

I take it your work is 99% chip level, then?

No doubt about that. Some can't even write/draw a datasheet correctly:

The STP19NM50N datasheet shows Cdss(V) having some bizarre kink, which I suspect is a graphical glitch in the output (a PDF editor could confirm how many line segments / beziers it's drawn with), but the fact remains, I measured it myself to be something fairly different.

The SPICE model (they don't have the 19NM50, but they do have the 28 or something -- datasheets are pretty much linear scaled up, so I consider this a justifiable surrogate, with respective adjustments) is a boring LEVEL=3 standard, with fixed drain capacitance. Sure, it will pass the switching speed test at the datasheet conditions (400V swing, 10-90% times), but the switching losses are preposterously optimistic, to say nothing of reverse recovery (if you have to deal with it). Not that SPICE ever quite got diode recovery (forward or reverse) right.

After measuring the actual capacitance, I went and modeled it (I ended up with a constant capacitor in parallel with two diodes with different EJ, M and CJO), and adjusted it against the time equivalent capacitance.

Cdg is modeled, but I can't really verify that unfortunately.

On the polar opposite of the spectrum, I've seen at least one Infineon model that's completely synthesized, no M's at all -- I assume it's very accurate, but it crawled so damned slowly that it was even more useless to me! I ended up simulating that with a competitor's LEVEL=3, just to get somewhere.

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com

Fortunately, 99% of my work is IC design. This means BSim3v3, BSim4 and VBIC, which have, usually, been very accurately modelled by the fab vendors use of 3rd party specialist modelling kits. Standed MOS1, MOS2 MOS3 are not very good.

Most things come at nuts on. There are same exceptions that do cause some bother though.

Kevin Aylward

- SuperSpice