inconsistent DCM delay from TRCE report ?

Hi all,

I am th* Tiopi = 0.909

  • net delay = 0.307
  • Tdcmino = -3.691 ... In the second :
  • Tiopi = 0.728
  • net delay = 0.246
  • Tdcmino = -3.993 ...

Because of the negative DCM-delay I will need to phase-shift the internal clk for my application, so I get the behaviour as in the standalone DLLs from e.g. VirtexE (meaning the delay from GCLK-input pad to IOB-flipflops is as good as zero). In order to do this right I need to have an idea of the real clk-delay through the whole path. btw : I use ISE5.2 SP3 with VirtexIIPro speedfiles version = ADVANCED

1.78 2003-05-08

Any thoughts on this ?

Thanks, Bart

================================================================================ Timing constraint: COMP "sdr_dq_green" OFFSET = OUT 2.500 nS BEFORE COMP "sdr_clk" ;

2 items analyzed, 0 timing errors detected. Maximum allowable offset is 5.242ns.

-------------------------------------------------------------------------------- Slack: 2.742ns (requirement - (clock arrival + clock path + data path)) Source: sdr_clk (PAD) Destination: sdr_dq_green (PAD) Source Clock: fpga_clk rising at 0.000ns Requirement: 5.019ns Data Path Delay: 2.623ns (Levels of Logic = 0) Clock Path Delay: -0.346ns (Levels of Logic = 3)

Clock Path: sdr_clk to i_sdr_ctlr_u_data_path_sdr_green_o_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) -------------------------------------------------

------------------- B13.I Tiopi 0.909 sdr_clk sdr_clk i_clk_dlls_sdram_ibufg_sys_clk DCM_X1Y1.CLKIN net (fanout=1) 0.307 i_clk_dlls_sdram_sys_clk DCM_X1Y1.CLK0 Tdcmino -3.691 i_clk_dlls_sdram_dll_int i_clk_dlls_sdram_dll_int BUFGMUX7P.I0 net (fanout=1) 0.769 i_clk_dlls_sdram_fpga_clk_out_o BUFGMUX7P.O Tgi0o 0.064 i_clk_dlls_sdram_bufg_clk_out i_clk_dlls_sdram_bufg_clk_out.GCLKMUX i_clk_dlls_sdram_bufg_clk_out J3.OTCLK1 net (fanout=611) 1.296 fpga_clk -------------------------------------------------

--------------------------- Total -0.346ns (-2.718ns logic, 2.372ns route)

Data Path: i_sdr_ctlr_u_data_path_sdr_green_o_3 to sdr_dq_green Location Delay type Delay(ns) Physical Resource Logical Resource(s) -------------------------------------------------

------------------- J3.PAD Tiockp 2.623 sdr_dq_green i_sdr_ctlr_u_data_path_sdr_green_o_3 i_sdr_ctlr_u_data_path_sdr_dq_io32/OBUFT sdr_dq_green -------------------------------------------------

--------------------------- Total 2.623ns (2.623ns logic,

0.000ns route) (100.0% logic, 0.0% route)

================================================================================ Timing constraint: COMP "sdr_dq_green" OFFSET = IN 5.770 nS AFTER COMP "sdr_clk" ;

1 item analyzed, 1 timing error detected. Maximum allowable offset is 5.370ns.

-------------------------------------------------------------------------------- Slack: -0.400ns (requirement - (data path - clock path - clock arrival)) Source: sdr_dq_green (PAD) Destination: i_sdr_ctlr_u_data_path_u_data_green_o_3 (FF) Destination Clock: fpga_clk rising at 0.000ns Requirement: 1.749ns Data Path Delay: 0.901ns (Levels of Logic = 0) Clock Path Delay: -1.248ns (Levels of Logic = 3)

Data Path: sdr_dq_green to i_sdr_ctlr_u_data_path_u_data_green_o_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) -------------------------------------------------

------------------- J3.ICLK1 Tiopick 0.901 sdr_dq_green sdr_dq_green i_sdr_ctlr_u_data_path_sdr_dq_io32/IBUF i_sdr_ctlr_u_data_path_u_data_green_o_3 -------------------------------------------------

--------------------------- Total 0.901ns (0.901ns logic,

0.000ns route) (100.0% logic, 0.0% route)

Clock Path: sdr_clk to i_sdr_ctlr_u_data_path_u_data_green_o_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) -------------------------------------------------

------------------- B13.I Tiopi 0.728 sdr_clk sdr_clk i_clk_dlls_sdram_ibufg_sys_clk DCM_X1Y1.CLKIN net (fanout=1) 0.246 i_clk_dlls_sdram_sys_clk DCM_X1Y1.CLK0 Tdcmino -3.993 i_clk_dlls_sdram_dll_int i_clk_dlls_sdram_dll_int BUFGMUX7P.I0 net (fanout=1) 0.615 i_clk_dlls_sdram_fpga_clk_out_o BUFGMUX7P.O Tgi0o 0.054 i_clk_dlls_sdram_bufg_clk_out i_clk_dlls_sdram_bufg_clk_out.GCLKMUX i_clk_dlls_sdram_bufg_clk_out J3.ICLK1 net (fanout=611) 1.102 fpga_clk -------------------------------------------------

--------------------------- Total -1.248ns (-3.211ns logic, 1.963ns route)

--------------------------------------------------------------------------------

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Bart De Zwaef
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