Hi,
I would like to generate a clock from a refclk according to the following function:
clk = refclk*(64/66)
I will implement this function in an VirtexII Pro FPGA and my first approach is to divide the refclk by 3 in logic and then use a DCM to multiply with 32/11.
clk = refclk*(1/3)*(64/22) clk = refclk/3*(32/11)
Will this work? The frequencies has to be locked to each other.
------ Patrik Eriksson