Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler

Hi group,

Are there any problems with chaining multiple instances of the clock doubler from this link together?

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(see section 6)

Clock rate variations preclude the use of DCMs (even in low frequency mode using CLKFX only).

Many thanks for your time.

Reply to
Dave
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Dave a écrit :

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Hello Look at the output waveform: this circuit generates a *pulse* on each transition of the input signal. If you chain a second circuit, it will generate pairs of pulses (about 2ns apart, from the circuit description) on each transition of the input signal, and so on. Your average output frequency will actually be 2**n (n being the number of pseudo-doublers in your chain) but your duty cycle will be almost random. Read "unusable"

Nicolas

Reply to
Nicolas Matringe

NO !! Do not cascade that frequency double circuit. As a single instant, the circuit is (or can be made to be) safe and reliable, but a cascade would generate garbage. Peter Alfke

Reply to
Peter Alfke

OK. Many thanks for the quick answers. I knew it couldn't be so easy...

Reply to
Dave

Dave-

With freq variations or even complete clock stop, you can still use DCMs, and use an sm based on an independent, reliable clock to measure the actual DCM output (not the LOCKED signal, which I found to be unreliable). If it locks up or starts producing bogus duty cycle, then follow the procedures for Reset.

I've had good luck with this approach.

-Jeff

Reply to
Jeff Brower

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What are you trying to do ?

Chain of a simple clock doubler is not practical, but there are other solutions.

eg If you need 8 clocks to spin a state engine, for each incomming edge, than that can be done. Create a Gated Ring Osc, counter and XOR CE, and clock the counter until chosen /N bit equals Fin. This gives a burst of edges, syncronised with the input signal, but they are not evenly spaced, or phase-located; You get (eg) 8 clocks for each input edge.

-jg

Reply to
Jim Granville

Hi Jeff,

Sounds interesting. Unfortunately, the input clock will sometimes be lower than 1MHz and the output must be > 24MHz so a DCM cannot be used at all.

I see there is a reset pin on the DCM. I assume the procedures for reset are to stop using the output clock when it is messed up, assert reset and wait for a good clock again before using teh output once more?

Many thanks,

Dave

Reply to
Dave

Hi Jim,

What is required is to generate 2x, 4x and 8x clocks from the input. Could be done using 3 DCMs (assuming in range inputs/outputs) each doing 2x.

The appropriate clock would then be selected and used.

Your method of generating 8 edges sounds cool but I think a regular clock will be required rather than a bursty one.

Cheers,

Dave

Reply to
Dave

You have not defined what 'clock rate variations' will be. A regular locked multiple is only possible with a regular referance IP. Wobble the IPs and the DCMs will chase their tail trying to follow.... So, you will need to nail down the dF and Slews (dF/dT) and also when it does, and does not, have to follow with 8x outputs - and then try some designs.

-jg

Reply to
Jim Granville

Hi Jim,

The input clock may be as low as 200 kHz and as high as 20-30MHz perhaps. The frequency will be fixed at a certain frequency while the system runs however (i.e. it is not going to swing around in that range!).

The issue is that 2x, 4x and 8x are required. The minimum output of the DCM when using CLKFX is 24MHz so 12MHz is the minimum input but downto 200kHz as input is required. Also, 1MHz is min input of DCM and lower freqs than this may be used. So, DCMs cannot be used.

Many thanks for your help,

Dave

Reply to
Dave

Dave schrieb:

If you can live with a few ns jitter you can digitally synthesize the clocks from an additional fast clock.

Kolja Sulimma

Reply to
Kolja Sulimma

Hi Kolja,

Do you mean take a fast clock and clock some counters to generate enables or something more fancy?

Dave

Reply to
Dave

Dave schrieb:

Just like that.

You measure the frequency with a counter and use the measured value to generate new clocks.

Also: Do you really need a 2x, 4x, 8x clock? Or is it sufficient, to have 2, 4 and 8 clock edges within each cycle of the original clock?

As your circuitry is able to run at 240MHz anyway (8x30Mhz) you can have a 240MHz circuit that waits for a rising edge of the input clock and then generates eight pulses set 4ns apart independent of the input frequency.

You can only use this if the timing of the results is not important.

Kolja

Reply to
Kolja Sulimma

DCM's can be used above 1 MHz with CLKFX only (no DLL outputs). You just need to increase the multiply factor on the first DCM, i.e. start with

32X and divide down to get 8X 4X 2X. Below 1 MHz you'd probably do best to use a constant high-speed clock and digitally generate the clock outputs if you can stand the jitter (1 cycle of the high-speed clock).

Its unlikely you'll find a single method to multiply the clock over the entire range of the circuit. Having a constant high-speed clock allows you to determine the input frequency and select the best method.

Reply to
Gabor

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