Memory generator IP core ISE Webpack

Greetings...

I have been trying to use a block memory component (in this case just a single port ROM to start with... will be adding a dual port RAM once I get this part working) in ISE Webpack 9.1i, generated of course by the Core Generator.

I'm quite sure that my syntax is correct; I have the component declared in my main vhdl module's architecture header, and an instance declared in the body with the ports mapped to the intended signals/ports in my main module. XST synthesizes this with no errors.

However, for some reason I'm finding that both the input and output signals connected with the ROM (addr in and data out) are always showing up as indeterminate in both simulation and implementation.

Is there any common reason why this might be?

Thanks, Steve

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Steve Battazzo
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