So I thought, "how hard can it be to download to a V2P7 part using the slave serial mode?"
Well, pretty hard.
I have a 'master' FPGA that loads a 'slave' FPGA using the slave serial programming mode. The download process will work over and over, then suddenly decide not to work. Then it doesn't work for a long time. Very flakey.
The master FPGA drives PGM_N, CCLK, and DIN to the slave using2.5V CMOS outputs. The signals all look clean, no over/undershoot, no glitches in the transition region, etc. The data setup/hold is over 100ns, the data is setup before the rising edge of CCLK and is held until after the falling edge. By default, the clock is held low and pulses high for about 70ns when new data is ready for the slave.
The master FPGA has very simple logic that interfaces to a PC. The PC can assert the PGM_N signal and can look at the status of INIT_N and DONE to monitor programmng status. The PC can also write a 32 bit word into the master which then serializes the data to the DIN and CCLK pins on the slave.
Things to note: 1) The download is flakey, but since it can succeed multiple times in a row, I'm pretty sure that the bit order of data being shifted into the slave FPGA is correct. 2) I've added logic to grab the output data using the output CCLK clock so the PC can verify that the data has not been corrupted. It always reads back correctly. 3) I've turned the 'debug' flag on in bitgen so I can look at the DOUT pin. When things work, I get lots of pulses out of DOUT, when download fails, DOUT will either pulse low once or pulse low multiple times, but stop pulsing before the download completes. 4) Occasionally, INIT_N is asserted by the FPGA before the download is done. 5) The data loads to the slave in bursts of 32 bits, ie, the PC sends a 32 bit word, the master serializes it, then everything waits while the PC realises it's done and loads the next word. It's about 150 usec between 'bursts'.3 & 4 lead me to believe the slave FPGA is receiving corrupted data or a bad clock occasionally, BUT... the signals look fine.
We have M[2:0] and HSWAP_EN pulled to 2.5V using 10K resistors. PWRDWN_N is floating as is VBATT. The JTAG signal are also pulled to static levels.
It almost acts like there's a floating pin - if it's in one state everything is fine, if it drifts or comes up in the 'wrong' state, the download fails.
Has anyone run into problems like this? My local FAE is stumped as am I.
Thanks for any insights!