FPGA Programming solution

Alfredo,

Two solutions in my knowledge,

Try Dynamic Partial reconfiguration, If you are using Xilinx FPGA's, try MicroBlaze as configuration controller. It may require a bit of effort from your side.

Use a Micro-controller as configuration controller, configuring the FPGA in Slave serial mode through Micro-Controller is far easier than emulating the functionality of PROM through Micro-controller.

Hope this helps /MH

If the functions of the two programs are so similar, is it possible to contain them in a single configuration?

For configuration with an external microcontroller, it's probably best to use "passive configuration" mode.

How fast do you need the configuration to load? It can take a long time when done with an external micro!!

For example, I use hand-optimised PIC assembler to load a compressed configuration to the smallest Altera Cyclone II. The PIC is clocked at 32MHz and controls only the clock signals. (The data is connected directly from the flash memory (an SD card) to the FPGA configuration data input).

Even in this "Formula 1" arrangement (with loop unrolling and with the SD card and FPGA configuration clock signals on the same PIC port to save one instruction of the loop), it takes about 0.3s to load the FPGA.

Mike

Hi again , the function is similar but the design is different. I mean , both are digital filters but they use different architectures.

1- Where can I read about Dynamic Partial ? I am not using a very large FPGA ( xc3s500e) so I dont know if a Microblaze processor would fit in. 2- I will study a bit more about Slave serial mode but I dont understand how this can help me choose which program I will load on the FPGA. 3- Programming time is not an issue since it will be programmed once or twice a month in the worst case. 4- Has anyone evaluate SystemBIST , is it expensive ? not really useful? unconvenient?

Thanks again , and sorry for my bad english.

I understand from

that Xilinx "slave serial" mode is equivalent to Altera "passive serial mode".

In this mode, the microcontroller loads the FPGA, so you have complete control in the microcontroller program of what data is sent to the FPGA as its configuration.

Mike

from

I think I will focus on Multi-Boot PROM , any experience with that?

Check SystemACE. It will configure a set of FPGAs from a compact flash card. You can select one of eight configurations stored on the card either by external signals or by registers that can be accessed by FPGA logic. The CF can also be writte by the FPGA to allow in system updates.

Regards,

Kolja Sulimma

No.

The keyword to search for in the Spartan3E data sheet is "Multiboot" if you want to have the program in flash and let the FPGA take care of it rather than hooking up an external micro. Both approaches will get you what you want.

With Xilinx FPGAs, the fastest solution with a micro is usually one of the SPI modes. And a fast micro, of course. A little PAL or another FPGA will be at least as fast. Maybe this is also true for Altera.

Let's race your SPI solution against my hand-optimised assembler!! :)

I have to warn you that my method transfers at a peak rate of one configuration bit every 375ns (three instruction cycles) and an average of about one bit every 420ns over each 512-byte block from the flash device. (There's a delay in requesting each block which would apply to any method).

If you use SPI, you'll first need to read the flash data into your processor. With byte-wide flash, you have an advantage there and may overtake me (although you'll use a lot more processor lines). With serial flash, it will take longer to read the data to your processor (unless you use another SPI controller for that) than it takes me to send it on the direct connection between my flash memory and the FPGA by just toggling the clocks.

With parallel flash memory, you could still use direct connection. This would waste all but one bit in each flash word, but that may not be significant if the flash memory is much larger than the FPGA configuration.

Mike

Ok , so here we are. We are evaluating between using a 16Mb PROM that you can use for Multi-boot ( USD $16) or doing it with a processor that would read all the programs from different Flash memories. In case we use the last one , I will evaluate wether use SPI or hand- optimised Assembler code.

What do you think of that?

The Xilinx Platform Flash with Revisioning is a great, simple way to do this. With a parallel interface, it's very fast, and it comes with JTAG in-system capability.

A lower cost alternative is Master SPI MultiBoot, which is available on the Spartan-3A series of FPGAs. Spartan-3E supports MultiBoot through parallel flash or Platform Flash. Spartan-3A can also do it with SPI flash and can support as many images as your flash will hold. See the Master SPI Mode and Reconfiguration and MultiBoot chapters in UG332

One restriction with SPI is that the first configuration always takes place at address 0. So, you may have to have a "Selector" bitstream that takes user input to decide whether to redirect to Application A or Application B.

You can see a simple example of this for the Spartan-3A Starter Kit on the Avnet Design Resource Center (sorry for the long URL)

Bryan

Alfreeeeed wrote:

Another scheme is to use one of the really cheap SST serial proms that is twice the size you need, and rig a select bit to the logic that instructs the PROm where to start reading from. These chips are not drop-in replacements for the standard download PROMs, but they are SO cheap that it pays for the extra components required.

Jon

I have a scheme that I have worked out to use the SST25VF010-20-4C-SAE chip, $0.98 in 100 piece quantity, that's a 1 MBit serial flash. They have several larger versions, like the 8 MBit one is ~$3.00 ! I use a pair of LVQ CMOS logic chips to send the correct instruction to the chip to prepare it to read from the beginning. It would require adding one additional chip to extend the number of programmable bits so you could select the starting location within the PROM to select the desired program. This requires no CPU whatsoever, and the 2 or 3 logic chips are tiny SSOP parts costing no more than $0.25 each. The SPROM can keep up with the Xilinx master-mode configuration clock, so you don't need to provide a special clock for it.

Jon

how about wiring the prom clock to a pin that can be used as a timer output, at startup you can use the pin as io and bitbang the prom the usual way to pick the right starting address and give it the right read commands, after that enable the pin as a timer output and run as fast as the timer will go...

-Lasse

Maybe that would work in some cases. The number of clocks would need to be well-defined (to match exactly the size of a data block). The micro would then need to discard the CRC which follows the data. (It needn't check it as the FPGA will check the CRC on the whole of the configuration).

In my case, the clock to the flash memory must be set before the clock to the FPGA (although they can be cleared at the same time), so a single signal won't work.

Mike

oh, I didn't notice you used an SD card, I was imagining a regular serial prom where you can just keep on clocking till you have enough bits.

-Lasse

Of course, an SD card wouldn't be first choice for storing the configuration, but the application is based on SD card, so it makes sense to fetch the configuration from there, too.

Mike

Looks like SPI Master Mode is the option. I am interested in Jon's alternative of putting a memory twice the size a program need. Any ideas how to implement this? BTW , I also need to program two FPGA with the same program so I would need to do daisy chain with a Spartan-3E.

So for my bad english and thanks

Alfred