Digital LP filter in multiplier free FPGA

Spatan

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depending what you need, one solution is very simple "digital integrator" its doable with only shift and add, there is some appnote or something at xilinx web, I used that in digital carrier frequency amplifier, and it did give actually very good filtering (for my application at least).

an example digital integrator source is appended

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--

-- 18 Bit Digital Integrator Feedback "multiplier"

-- constant 1 / 256 (fixed, no choices implemented)

-- Tested and working. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;

entity integrator_18bit is Port ( rst : in std_logic; clk : in std_logic; din : in std_logic_vector(17 downto 0); -- Input: 18 Bit Unsigned INTEGER k : in std_logic_vector(3 downto 0); -- multiplier select (not implemented) dout : out std_logic_vector(17 downto 0) -- Output: 18 Bit Unsigned INTEGER ); end integrator_18bit;

architecture Behavioral of integrator_18bit is

signal acc : std_logic_vector(25 downto 0); signal vi_minus_vo : std_logic_vector(25 downto 0); signal vi_minus_vo_sign_extended : std_logic_vector(7 downto 0);

begin -- Microblaze "endian" conversion dout(0)

See zipfile in abse. If I post it here, the formatting gets lunched.

John

Spatan

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Thanks John. Unfortunately I've got text only news server access, any chance in emailing? (remove .nospam).

Cheers,

Mark.

OK, done, I think.

John

Oops, K1 should be 4, 1/16. File got scrambled somehow.

John

Hi Mark,

I can help you out with this by automatically generating VHDL for an FIR implementation for your filter that uses shifts and adds.

Please post the following details:

Do you want the filter to run at 12MHz (i.e. full-parallel) or do you have a faster clock available that could be used to share hardware over multiple clock cycles?

Is the filter single-rate or are you decimating?

Input bit-width?

Signed/unsigned input?

Quantised filter coefficients (integers ideally but fixed-point will do) or more detailed spectral requirements (what -dB gain at 3MHz, pass-band ripple etc., start rolling off at what freq, stop rolling of at what freq. etc.)

Cheers,

Ken

You didn't say how sharp your cutoff needs to be, or how much gain ripple you can tolerate. You might consider a pipelined multiplier design. This will result in very high clock rates, permitting one multiplier to handle 8-16 coefficients. Several multipliers can be used in parallel to increase the number of coefficients even further. Xilinx has numerous ap notes on digital filtering techniques. Here is a good review of the topic:

Tom

Thanks John. I'm not really sure how to tweek this for my system, but very interesting stuff nonetheless. I decided in the end to go for a 'rolling average' type filter (rectangular) with 16 taps, and this seems to be working quite nicely so I think I'll stick with this.

Regards,

Mark.

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ripple

Hi Ken,

Well I've gone for a rolling average filter at the moment, but the specs are:

I've got a 65MHz clock and currently dividing by 6 to give 13MHz.

Single rate so far.

Unsigned.

-3db @ 3MHz, 4th order Butterworth type roll-off ideally, unity gain otherwise.

Thanks!

Mark.

Spatan

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Thanks Tom! Interesting stuff.

Mark.

Thanks! I'll have a look at this.

Mark.

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Unsigned

Hi Mark,

OK - do you want the filter to run at 13MHz (I thought you said 12 before?) and use more area or run at 65MHz and use less area?

I can generate something immediately for you that would run at 13MHz.

Cheers,

Ken

Dear Mark, Seems to be a half-band filter (half of the Nyquist freq of 6 MHz) so, when you use a FIR filter you can leave out half of the taps. The Xilinx core generator can generate a nice filter for you. For the tap values use some FIR design tool, look at

Markp,

You can use a distributed arithmetic filter if you take advantage of the higher available clocks. With a 65 MHz clock, you have 5 clocks (13 MHz is 1/5 of 65, not 1/6) per pixel available. By using a two bit parallel distributed arithmetic filter you can get a quite compact filter. DA 'hides' the coefficient multiplies by summing all the bit partial products from all the taps before doing the shift-accumulate. The Spartan II has DLLs in it that can easily be used to double the 65 MHz clock to obtain a

markp wrote:

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

But previously you said a sharp cutoff. You won't get that with an average. If your clock is at 12 MHz, and you want an LPF with a 3MHz cutoff, I would use a half-band filter.

All even coefficients will be 0 (with the exception of a0 at 0.5). Also, the filter is symmetric in the time domain allowing you to use a folded ladder topology to use half the "multipliers".

This will give you a response that's skew symmetric around fs/4.

It would seem that if the coefficients are constants it would not be hard to generate the appropriate shift and add hardware, pipelined as appropriate. Presumably you could use adders and subtractors, and the design could be optimized toward minimizing the number of adder/subtractor stages. (I think that can be done, but I haven't tried to do it.)

-- glen

See for one product that can do exactly this (and more). You can for example create multiplier-free filters in two styles with optional pipelining.

There are many other products in the marketplace for filter code generation; just look around.

Disclaimer: I work for The MathWorks.

Hi Mark,

If you need synthesizable VHDL, testbenches etc, our software Tyd-IP Code Generator and ONEoverT Digital Filter Designer will give you all you need. There are other development packages out there also. Have a look around to make sure you get exactly what you need.

Good Luck Alan

Spatan

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Thanks Henk, this seems a nice tool. I'll have a play!

Mark.

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