This is the module with the RLOCs. I'm just hacking away here, so it's not perfect code. The long list of RLOC/BEL attributes is there because I haven't been able to figure out how to integrate that into the "generate" portion of the code. I don't see a way to construct the attribute string --even with the V2001 (*...*) attribute format. Yet another case for VHDL :-(
Code below.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian
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// Generates an SRL-based shift register of the desired word width and delay (in clocks) // A minimum delay of 2 clocks is required, as the output is registered. // "Q15_OUT" is the cascading SRL output, used to get 16 clocks of delay, regardless // of the DELAY setting. //
module SRL_DLY #(parameter WIDTH = 8, DELAY = 2) ( input wire CLK, input wire [WIDTH - 1:0] IN, output wire [WIDTH - 1:0] Q_OUT, output wire [WIDTH - 1:0] Q15_OUT );
localparam D = DELAY - 2;
wire [WIDTH - 1:0] qw;
genvar i;
generate for(i=0; i < WIDTH; i=i+1) begin:BIT SRLC16 SRL(.Q(qw[i]), .Q15(Q15_OUT[i]), .A3(D[3]), .A2(D[2]), .A1(D[1]), .A0(D[0]), .CLK(CLK), .D(IN[i])); FD DFF (.Q (Q_OUT[i]), .C (CLK), .D (qw[i])); end endgenerate
// RLOC the SRLC16 primitives // //synthesis attribute RLOC of BIT[0].SRL is X0Y0 //synthesis attribute BEL of BIT[0].SRL is F //synthesis attribute RLOC of BIT[1].SRL is X0Y0 //synthesis attribute BEL of BIT[1].SRL is G
//synthesis attribute RLOC of BIT[2].SRL is X0Y1 //synthesis attribute BEL of BIT[2].SRL is F //synthesis attribute RLOC of BIT[3].SRL is X0Y1 //synthesis attribute BEL of BIT[3].SRL is G
//synthesis attribute RLOC of BIT[4].SRL is X0Y2 //synthesis attribute BEL of BIT[4].SRL is F //synthesis attribute RLOC of BIT[5].SRL is X0Y2 //synthesis attribute BEL of BIT[5].SRL is G
//synthesis attribute RLOC of BIT[6].SRL is X0Y3 //synthesis attribute BEL of BIT[6].SRL is F //synthesis attribute RLOC of BIT[7].SRL is X0Y3 //synthesis attribute BEL of BIT[7].SRL is G
//synthesis attribute RLOC of BIT[8].SRL is X0Y4 //synthesis attribute BEL of BIT[8].SRL is F //synthesis attribute RLOC of BIT[9].SRL is X0Y4 //synthesis attribute BEL of BIT[9].SRL is G
//synthesis attribute RLOC of BIT[10].SRL is X0Y5 //synthesis attribute BEL of BIT[10].SRL is F //synthesis attribute RLOC of BIT[11].SRL is X0Y5 //synthesis attribute BEL of BIT[11].SRL is G
//synthesis attribute RLOC of BIT[12].SRL is X0Y6 //synthesis attribute BEL of BIT[12].SRL is F //synthesis attribute RLOC of BIT[13].SRL is X0Y6 //synthesis attribute BEL of BIT[13].SRL is G
//synthesis attribute RLOC of BIT[14].SRL is X0Y7 //synthesis attribute BEL of BIT[14].SRL is F //synthesis attribute RLOC of BIT[15].SRL is X0Y7 //synthesis attribute BEL of BIT[15].SRL is G
// RLOC the FF's // //synthesis attribute RLOC of DFF[0] is X0Y0 //synthesis attribute BEL of DFF[0] is FFX //synthesis attribute RLOC of DFF[1] is X0Y0 //synthesis attribute BEL of DFF[1] is FFY
//synthesis attribute RLOC of DFF[2] is X0Y1 //synthesis attribute BEL of DFF[2] is FFX //synthesis attribute RLOC of DFF[3] is X0Y1 //synthesis attribute BEL of DFF[3] is FFY
//synthesis attribute RLOC of DFF[4] is X0Y2 //synthesis attribute BEL of DFF[4] is FFX //synthesis attribute RLOC of DFF[5] is X0Y2 //synthesis attribute BEL of DFF[5] is FFY
//synthesis attribute RLOC of DFF[6] is X0Y3 //synthesis attribute BEL of DFF[6] is FFX //synthesis attribute RLOC of DFF[7] is X0Y3 //synthesis attribute BEL of DFF[7] is FFY
//synthesis attribute RLOC of DFF[8] is X0Y4 //synthesis attribute BEL of DFF[8] is FFX //synthesis attribute RLOC of DFF[9] is X0Y4 //synthesis attribute BEL of DFF[9] is FFY
//synthesis attribute RLOC of DFF[10] is X0Y5 //synthesis attribute BEL of DFF[10] is FFX //synthesis attribute RLOC of DFF[11] is X0Y5 //synthesis attribute BEL of DFF[11] is FFY
//synthesis attribute RLOC of DFF[12] is X0Y6 //synthesis attribute BEL of DFF[12] is FFX //synthesis attribute RLOC of DFF[13] is X0Y6 //synthesis attribute BEL of DFF[13] is FFY
//synthesis attribute RLOC of DFF[14] is X0Y7 //synthesis attribute BEL of DFF[14] is FFX //synthesis attribute RLOC of DFF[15] is X0Y7 //synthesis attribute BEL of DFF[15] is FFY
endmodule