I have some problem detecting the full and empty conditions in an asynchronous FIFO design. Hope any of you can help.
Assume wr_clk is slower than the rd_clk. The rd_ptr is synchronized to the wr_clk domain to generate the full flag in wr_clk (slow) domain while the wr_ptr is synchronized to the rd_clk domain to generate the empty flag in rd_clk (fast) domain.
Say, on every 8th wr_clk, I generate a "wr_enable" signal. I write to the FIFO and increment the write pointer whenever the "wr_enable" is true. Assume the depth of the FIFO to be 4. I have written 3 FIFO locations and my write pointer points to the last FIFO location at the same time the 3rd location is written. Now when I write to the last available (4th) FIFO location, full flag should be asserted. But now when should it be deasserted?
- Whenever the read and write pointers are equal (irrespective of "wr_enable" signal) or 2. when the read and write pointers are equal and "wr_enable" is true??
Please direct if any of you have any good information on asynchronous FIFO design. Also is it possible to synchronize pointers from a faster clk domain to slowr clk domain?