Resetting FIFO

Hello people,

when having a look at the specification of FPGA integrated FIFOs (Altera Cyclone devices, Lattice ECP devices) which are built up of integrated RAM and some logic there is nothing said about how to reset a FIFO suddenly while working.

Let us assume the FIFO has a wrclk (=50MHz) and a rdclk (=120MHz).

What does happen if a synchronous reset signal is generated for one

120MHz clock cycle and is applied to the asynchronous fifo reset input ? Does the fifo reset correctly on both fifo buffers? What about the read and write flags during this synchronous reset ? Do they have to be inactive ?

Or could it be a better strategy to make the reset signal longer than just one clock cycle ? To which clock should this reset signal be synchronous ?

When starting up the FPGA the RESET applied to the FIFOs is long enough so that there is no problem but I would like to clarify the situation of an intermediate RESET.

Thanks for your suggestions.

Kind regards André

Reply to
ALuPin
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Cyclone

Resetting a FIFO is tough because of the two clock domains. I made a robust circuit to do this once; it was a pair of concurrent state machines in different clock domains. An easier and fairly robust way would be to use the "aysynchronous reset, synchronous clear" circuit in both domains. This consists of two flops in each domain. When you want to reset, set both flops using the asynchronous preset. Then the first flop clears itself synchronously, because the D input is tied to zero. The second flop is connected to the first, so it clears on the next cycle synchronously. The output of that is connected to the async reset of the read or write side of the FIFO. I know this textual description may not be clear, but by using a pair of these you can reset both sides of the FIFO at the same time, but make sure that the reset is deasserted synchronously to the clocks on either side to avoid setup violations.

-Kevin

Reply to
Kevin Neilson

(Altera Cyclone

working.

input ?

I haven't seen the built-in FIFO's yet, but in the Xilinx CoreGen FIFO's the reset is always asynchronous for the dual-clocked FIFO's. The required pulse width of the reset input is very short and depends only on the reset timing parameter of the CLB flip-flops.

just one

Generally resetting the FIFO does nothing to the memory array, but just asynchronously resets the pointers and flag logic. Generally making the reset synchronous to the write side is safer, assuming the logic prevents read pointers from changing when the FIFO is empty. In the case of CoreGen FIFO's, the EMPTY and FULL flags are both asserted during reset, which prevents writes or reads from affecting the pointers until each flag has been clocked into its proper state. This is a little like the reset flip-flop approach Kevin mentioned.

enough

of

Reply to
Gabor

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