Hello people,
when having a look at the specification of FPGA integrated FIFOs (Altera Cyclone devices, Lattice ECP devices) which are built up of integrated RAM and some logic there is nothing said about how to reset a FIFO suddenly while working.
Let us assume the FIFO has a wrclk (=50MHz) and a rdclk (=120MHz).
What does happen if a synchronous reset signal is generated for one
120MHz clock cycle and is applied to the asynchronous fifo reset input ? Does the fifo reset correctly on both fifo buffers? What about the read and write flags during this synchronous reset ? Do they have to be inactive ?Or could it be a better strategy to make the reset signal longer than just one clock cycle ? To which clock should this reset signal be synchronous ?
When starting up the FPGA the RESET applied to the FIFOs is long enough so that there is no problem but I would like to clarify the situation of an intermediate RESET.
Thanks for your suggestions.
Kind regards André